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DLPC900 Datasheet(PDF) 5 Page - Texas Instruments |
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DLPC900 Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 72 page  DLPC900 www.ti.com DLPS037A – OCTOBER 2014 – REVISED AUGUST 2015 Initialization Pin Functions PIN I/O CLK I/O TYPE DESCRIPTION POWER SYSTEM NAME NUMBER Power-On Sense is an active high signal with hysteresis, that is generated from an external voltage monitor circuit. This signal should be driven active high when all the controller I4 supply voltages have reached 90% of their specified POSENSE P22 VDD33 Async H minimum voltage. This signal should be driven inactive low after the falling edge of PWRGOOD as shown in Figure 2 Power Up and Power Down timing requirements. See also System Power-Up Sequence. Power Good is an active high signal with hysteresis that is provided from an external voltage monitor circuit. A high value indicates all power is within operating voltage specifications and the system is safe to exit its RESET state. A transition from high to low is used to indicate that the DLPC900 and DMD supply voltage will drop below their rated minimum level. This transition must occur prior to the supply voltage drop as specified. During this interval, POSENSE must remain active high. PWRGOOD serves as an early I4 warning of an imminent power loss condition. A DMD park PWRGOOD T26 VDD33 Async H followed by a full controller reset is performed by the DLPC900 to protect the DMD. The minimum de-assertion time is used to protect the input from glitches. After the park sequence is complete, the DLPC900 will be held in its RESET state as long as PWRGOOD is low. PWRGOOD must be driven high for normal operation. The DLPC900 will acknowledge PWRGOOD as active once it’s been driven high for its specified minimum time. See Figure 2 Power Up and Power Down timing requirements. See also System Power-Up Sequence. General purpose active low reset output signal. This output is driver low immediately after POSENSE is externally driven low, placing the system in RESET and remains low while POSENSE remains low. EXT_ARSTZ will continue to be EXT_ARSTZ T24 VDD33 O2 Async held low after POSENSE is driven high and released by the controller firmware. EXT_ARSTZ is also driven low approximately 5 µs after the detection of a PWRGOOD or any internally generated reset. In all cases, it will remain active for a minimum of 2 ms. Controller active low reset output signal. This output is driven low immediately after POSENSE is externally driven low and remains low while POSENSE remains low. CTRL_ARSTZ will continue to be held low after POSENSE is driven high CTRL_ARSTZ T25 VDD33 O2 Async and released by the controller firmware. CTRL_ARSTZ is also optionally asserted low approximately 5us after the detection of a PWRGOOD or any internally generated reset. In all cases it will remain active for a minimum of 2 ms. Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: DLPC900 |
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