 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
DLP9500 Datasheet(PDF) 10 Page - Texas Instruments |
|
|
||||||||||||||||||||||||||||||
DLP9500 Datasheet(HTML) 10 Page - Texas Instruments |
|
|
10 / 54 page  DLP9500 DLPS025C – AUGUST 2012 – REVISED SEPTEMBER 2015 www.ti.com Pin Functions (continued) PIN (1) TYPE DATA INTERNAL TERM TRACE SIGNAL CLOCK DESCRIPTION (I/O/P) RATE (2) (3) (MILS) NAME NO. DATA CLOCKS Differentially DCLK_AN D10 Input LVCMOS — — 325.8 terminated – 100 Ω Input data bus A Clock (2x LVDS) Differentially DCLK_AP D8 Input LVCMOS — — 319.9 terminated – 100 Ω Differentially DCLK_BN AJ11 Input LVCMOS — — 318.92 terminated – 100 Ω Input data bus B Clock (2x LVDS) Differentially DCLK_BP AJ9 Input LVCMOS — — 318.74 terminated – 100 Ω Differentially DCLK_CN C23 Input LVCMOS — — 252.01 terminated – 100 Ω Input data bus C Clock (2x LVDS) Differentially DCLK_CP C21 Input LVCMOS — — 241.18 terminated – 100 Ω Differentially DCLK_DN AJ23 Input LVCMOS — — 252.01 terminated – 100 Ω Input data bus D Clock (2x LVDS) Differentially DCLK_DP AJ21 Input LVCMOS — — 241.18 terminated – 100 Ω DATA CONTROL INPUTS Differentially SCTRL_AN J3 Input LVCMOS DDR DCLK_A 608.14 Serial control for terminated – 100 Ω data bus A (2x Differentially LVDS) SCTRL_AP J5 Input LVCMOS DDR DCLK_A 607.45 terminated – 100 Ω Differentially SCTRL_BN AF4 Input LVCMOS DDR DCLK_B 698.12 Serial control for terminated – 100 Ω data bus B (2x Differentially LVDS) SCTRL_BP AF2 Input LVCMOS DDR DCLK_B 703.8 terminated – 100 Ω Differentially SCTRL_CN E23 Input LVCMOS DDR DCLK_C 232.46 Serial control for terminated – 100 Ω data bus C (2x Differentially LVDS) SCTRL_CP E21 Input LVCMOS DDR DCLK_C 235.21 terminated – 100 Ω Differentially SCTRL_DN AG23 Input LVCMOS DDR DCLK_D 235.53 Serial control for terminated – 100 Ω data bus D (2x Differentially LVDS) SCTRL_DP AG21 Input LVCMOS DDR DCLK_D 235.66 terminated – 100 Ω SERIAL COMMUNICATION AND CONFIGURATION SCPCLK AE1 Input LVCMOS — pull-down — Serial port clock 324.26 SCPDO AC3 Output LVCMOS — — SCP_CLK Serial port output 281.38 SCPDI AD2 Input LVCMOS — pull-down SCP_CLK Serial port input 261.55 SCPEN AD4 Input LVCMOS — pull-down SCP_CLK Serial port enable 184.86 PWRDN B4 Input LVCMOS — pull-down — Device reset 458.78 MODE_A J1 Input LVCMOS — pull-down — 471.57 Data bandwidth mode select MODE_B G1 Input LVCMOS — pull-down — 521.99 10 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: DLP9500 |
Similar Part No. - DLP9500 |
|
Similar Description - DLP9500 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
