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DLP5500BFYA Datasheet(PDF) 10 Page - Texas Instruments |
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DLP5500BFYA Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 46 page  From Output Under Test Tester Channel LOAD CIRCUIT C = 50 pF C = 5 pF for Disable Time L L RL DLP5500 DLPS013F – APRIL 2010 – REVISED MAY 2015 www.ti.com 8.5 Thermal Information DLP5500 THERMAL METRIC FYA (CPGA) UNIT 149 PINS Thermal resistance from active array to specified point on case (TP1)(1) 0.6 °C/W (1) For more information, see Micromirror Array Temperature Calculation. 8.6 Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT High-level output voltage(1), See VOH VCC = 3.0 V, IOH = –20 mA 2.4 V Figure 2 Low-level output voltage(1), See VOL VCC = 3.6 V, IOL = 15 mA 0.4 V Figure 2 IOZ High impedance output current(1) VCC = 3.6 V 10 µA IIL Low-level input current(1) VCC = 3.6 V, VI = 0 V –60 µA IIH High-level input current(1) VCC = 3.6 V, VI = VCC 200 µA ICC Current into VCC pin VCC = 3.6 V, 750 mA ICCI Current into VOFFSET pin (2) VCCI = 3.6 V 450 mA ICC2 Current into VCC2 pin VCC2 = 8.75V 25 mA ZIN Internal Differential Impedance 95 105 Ω Line Differential Impedance (PWB ZLINE 90 100 110 Ω or Trace) CI Input capacitance(1) f = 1 MHz 10 pF CO Output capacitance(1) f = 1 MHz 10 pF CIM Input capacitance for f = 1 MHz 160 210 pF MBRST[0:15] pins (1) Applies to LVCMOS pins only (2) Exceeding the maximum allowable absolute voltage difference between VCC and VCCI may result in excess current draw. (Refer to Absolute Maximum Ratings for details) Figure 2. Measurement Condition for LVCMOS Output 10 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: DLP5500 |
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