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SI4709 Datasheet(PDF) 5 Page - Silicon Laboratories |
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SI4709 Datasheet(HTML) 5 Page - Silicon Laboratories |
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5 / 8 page  AN350 Rev. 0.2 5 Figure 3. Two Layer Stackup Figure 4. Four Layer Stackup 2.5. Si4708/09 2.5 x2.5 mm Design Checklist The following design checklist summarizes the guidelines presented in this section: Place bypass caps C1, C2, and C3 as close as possible to the supply and ground pins. Place a VIA connecting C1, C2, and C3 to the power supplies such that the cap is between the Si4708/09 and the VIA. Route a wide, low inductance return current path from the C1, C2, and C3 to the Si4708/09 GND pins. Place C4 as close as possible to FMI pin 2 and RFGND pin 3. Place a VIA connecting C4 to FMI on another layer as needed such that the cap is between Si4708/09 and the VIA. Place the series termination resistors R2–R6, as close to the host controller as possible. Place a ground plane under the device as shown in Figure 3, “Two Layer Stackup” or Figure 4, “Four Layer Stackup”. Place a local ground plane directly under the device for designs in which a continuous ground plane is not possible. Required for Si4709: Place R1 or C5 on opposite side of the PCB as the Si4709 for noise suppression. Place the VIA as close to pin 15 as possible and route the GPO trace to the system controller on this layer. Route all traces to minimize inductive and capacitive coupling by keeping digital traces away from analog and RF traces, minimizing trace length, minimizing parallel trace runs, and keeping current loops small. Route all GND (including RFGND) pins to the ground pad. The ground pad should be connected to the ground plane by using multiple VIAs to minimize ground potential differences. Route power to the Si4708/09 by trace, ensuring that each trace is rated to handle the required current. Do not route signal traces on the ground layer directly under the Si4708/09. Do not route signal traces under the Si4708/09 without a ground plane between the Si4708/09 and signal trace. Do not route digital or RF traces over breaks in the ground plane. Do not route digital signals or reference clock traces near the VCO pin 1 and 16 or the LOUT/ROUT output pin 13 and 12. Do not route VCO pin 1 and 16 (NC). These pins must be left floating to guarantee proper operation. Flood the primary and secondary layers with ground and place stitching VIAs. Place the Si4708/09 close to the antenna(s) to minimize antenna trace length and capacitance and to minimize inductive and capacitive coupling. This recommendation must be followed for optimal device performance. Route the antenna trace over an unobstructed ground plane to minimize antenna loop area and inductive coupling. Design, place, and route other circuits such that radiation in the band of interest is minimized. LAYER 2 – GROUND LAYER 1 – PRIMARY LAYER 1 – PRIMARY LAYER 2 – GROUND LAYER 3 – ROUTE LAYER 4 – SECONDARY |
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