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SL2305ZI-1HT Datasheet(PDF) 6 Page - Silicon Laboratories |
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SL2305ZI-1HT Datasheet(HTML) 6 Page - Silicon Laboratories |
6 / 11 page Rev 2.1, October 22, 2007 Page 6 of 11 SL2305 Switching Specifications: Unless otherwise stated VDD=3.3V+/-10% and both C and I Grades Notes: 1. For the given maximum loading conditions. See CL in Operating Conditions Table. 2. Parameter is guaranteed by design and characterization. Not 100% tested in production. Symbol Description Condition Min Max Unit FMAX1 Maximum Frequency (Input=Output ) [1] All Active PLL Modes High drive (-1H). All outputs CL=15pF 10 140 MHz High drive (-1H), All outputs CL=30pF 10 100 MHz Standard drive, (-1), All outputs CL=15pf 10 100 MHz Standard drive, (-1), All outputs CL=30pf 10 66 MHz INDC Input Duty Cycle Measured at 1.4V, Fout=66MHz, CL=15pF 30 70 % OUTDC1 Output Duty Cycle Measured at 1.4V, Fout ≥50MHz, CL=15pF [2] 40 60 % OUTDC2 Output Duty Cycle Measured at 1.4V, Fout ≤50MHz, CL=15pF [2] 45 55 % tr/f Rise, Fall Time (3.3V) (Measured at: 0.8 to 2.0V) [2] High drive (-1H), CL=10pF – 1.5 ns High drive (-1H), CL=30pF – 1.8 ns Standard drive (-1), CL=10pF – 2.2 ns Standard drive (-1), CL=30pF – 2.5 ns t1 Output-to-Output Skew (Measured at VDD/2) [2] All outputs CL=0 or equally loaded, -1 or -1H drives – 150 ps t2 Product-to-Product Skew (Measured at VDD/2) [2] All outputs CL=0 or equally loaded, -1 or -1H drives – 400 ps t3 Delay Time, CLKIN Rising Edge to CLKOUT Rising Edge Measured at VDD/2 [2] –220 220 ps tPLOCK PLL Lock Time Time from 90% of VDD to valid clocks on all the output clocks [2] – 1.0 ms CCJ Cycle-to-cycle Jitter Fin=Fout=66 MHz, <CL=15pF, -1H drive [2] – 140 ps Fin=Fout=66 MHz, <CL=15pF, -1 drive – 150 ps Fin=Fout=66 MHz, <CL=30pF, -1H drive – 160 ps Fin=Fout=66 MHz, <CL=30pF, -1 drive – 170 ps |
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