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LMK04806 Datasheet(PDF) 10 Page - Texas Instruments |
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LMK04806 Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 139 page  LMK04803, LMK04805, LMK04806, LMK04808 SNAS489K – MARCH 2011 – REVISED DECEMBER 2014 www.ti.com Electrical Characteristics (continued) 3.15 V ≤ VCC ≤ 3.45 V, -40 °C ≤ TA ≤ 85°C. Typical values represent most likely parametric norms at VCC = 3.3 V, TA = 25°C, at the Recommended Operating Conditions at the time of product characterization and are not specified. (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Charge pump current vs. ICPout2%TEMP 4% Temperature variation ICPout2TRI Charge pump leakage 0.5 V < VCPout2 < VCC - 0.5 V 10 nA PLL 1/f Noise at 10 kHz offset(8) PLL2_CP_GAIN = 400 µA -118 PN10kHz Normalized to dBc/Hz PLL2_CP_GAIN = 3200 µA -121 1 GHz output frequency PLL2_CP_GAIN = 400 µA -222.5 PN1Hz Normalized Phase Noise Contribution(9) dBc/Hz PLL2_CP_GAIN = 3200 µA -227 INTERNAL VCO SPECIFICATIONS LMK04803 1840 2030 LMK04805 2148 2370 fVCO VCO tuning range MHz LMK04806 2370 2600 LMK04808 2750 3072 Fine tuning sensitivity (The range displayed in the typical column indicates the lower sensitivity is KVCO typical at the lower end of the tuning LMK04808 20 to 36 MHz/V range, and the higher tuning sensitivity is typical at the higher end of the tuning range). After programming R30 for lock, no Allowable Temperature Drift for | ΔTCL| changes to output configuration are 125 °C Continuous Lock(13) (5) permitted to ensure continuous lock CLKout CLOSED LOOP JITTER SPECIFICATIONS USING a COMMERCIAL QUALITY VCXO(14) Offset = 1 kHz -122.5 Offset = 10 kHz -132.9 LMK04808 Offset = 100 kHz -135.2 fCLKout = 245.76 MHz Offset = 800 kHz -143.9 L(f)CLKout SSB Phase noise dBc/Hz Offset = 10 MHz; LVDS -156.0 Measured at clock outputs Value is average for all output types(15) Offset = 10 MHz; LVPECL 1600 -157.5 mVpp Offset = 10 MHz; LVCMOS -157.1 LMK04803(15) BW = 12 kHz to 20 MHz 112 fCLKout = 245.76 MHz BW = 100 Hz to 20 MHz 121 Integrated RMS jitter LMK04805(15) BW = 12 kHz to 20 MHz 113 fCLKout = 245.76 MHz JCLKout BW = 100 Hz to 20 MHz 122 Integrated RMS jitter LVDS/LVPECL/ fs rms LMK04806(15) BW = 12 kHz to 20 MHz 115 LVCMOS fCLKout = 245.76 MHz BW = 100 Hz to 20 MHz 123 Integrated RMS jitter LMK04808(15) BW = 12 kHz to 20 MHz 111 fCLKout = 245.76 MHz BW = 100 Hz to 20 MHz 123 Integrated RMS jitter (13) Maximum Allowable Temperature Drift for Continuous Lock is how far the temperature can drift in either direction from the value it was at the time that the R30 register was last programmed, and still have the part stay in lock. The action of programming the R30 register, even to the same value, activates a frequency calibration routine. This implies the part will work over the entire frequency range, but if the temperature drifts more than the maximum allowable drift for continuous lock, then it will be necessary to reload the R30 register to ensure it stays in lock. Regardless of what temperature the part was initially programmed at, the temperature can never drift outside the frequency range of -40 °C to 85 °C without violating specifications. (14) VCXO used is a 122.88 MHz Crystek CVHD-950-122.880. (15) fVCO = 2949.12 MHz, PLL1 parameters: FPD1 = 1.024 MHz, ICP1 = 100 μA, loop bandwidth = 10 Hz. 122.88 MHz Crystek CVHD- 950–122.880. PLL2 parameters: PLL2_R = 1, FPD2 = 122.88 MHz, ICP2 = 3200 μA, C1 = 47 pF, C2 = 3.9 nF, R2 = 620 Ω, PLL2_C3_LF = 0, PLL2_R3_LF = 0, PLL2_C4_LF = 0, PLL2_R4_LF = 0, CLKoutX_Y_DIV = 12, and CLKoutX_ADLY_SEL = 0. 10 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: LMK04803 LMK04805 LMK04806 LMK04808 |
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