LMK03806_15 datasheet(11/66 Pages) TI1

Part #	LMK03806

Description	Ultra Low Jitter Clock Generator With 14 Programmable Outputs

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LMK03806

www.ti.com

SNAS522I – SEPTEMBER 2011 – REVISED NOVEMBER 2015

Electrical Characteristics (continued)

3.15 V

≤ VCC ≤ 3.45 V, -40 °C ≤ TA ≤ 85 °C, Junction Temperature TJ ≤ 125 °C.

Typical values represent most likely parametric norms at VCC = 3.3 V, TA = 25 °C, at Recommended Operating Conditions at

the time of product characterization and are not ensured.

(1)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

PLL PHASE DETECTOR AND CHARGE PUMP SPECIFICATIONS

fPD

Phase detector frequency

155

MHz

VCPout=VCC/2, PLL_CP_GAIN = 0

100

µA

VCPout=VCC/2, PLL_CP_GAIN = 1

400

µA

ICPoutSOURCE

PLL charge pump source current

VCPout=VCC/2, PLL_CP_GAIN = 2

1600

µA

VCPout=VCC/2, PLL_CP_GAIN = 3

3200

µA

VCPout=VCC/2, PLL_CP_GAIN = 0

–100

µA

VCPout=VCC/2, PLL_CP_GAIN = 1

–400

µA

ICPoutSINK

PLL charge pump sink current

VCPout=VCC/2, PLL_CP_GAIN = 2

–1600

µA

VCPout=VCC/2, PLL_CP_GAIN = 3

–3200

µA

ICPout%MIS

Charge pump sink/source mismatch

VCPout=VCC/2, TA = 25 °C

3%

10%

Magnitude of charge pump current vs.

0.5 V < VCPout < VCC – 0.5 V

ICPoutVTUNE

4%

charge pump voltage variation

TA = 25 °C

Charge pump current vs. temperature

ICPout%TEMP

4%

variation

ICPoutTRI

Charge pump leakage

0.5 V < VCPout < VCC – 0.5 V

10

nA

PLL 1/f noise at 10 kHz offset(12).

PLL_CP_GAIN = 400 µA

–118

dBc/Hz

PN10kHz

Normalized to

PLL_CP_GAIN = 3200 µA

–121

dBc/Hz

1-GHz output frequency

PLL_CP_GAIN = 400 µA

–222.5

dBc/Hz

PN1Hz

Normalized phase noise contribution(13)

PLL_CP_GAIN = 3200 µA

–227

dBc/Hz

1-kHz Offset

–93

dBc/Hz

PLL phase noise

(Assumes a very wide bandwidth,

10 kHz

–103

dBc/Hz

L(f)

noiseless crystal, 2500-MHz output

100-kHz Offset

–116

dBc/Hz

frequency, and 25-MHz phase detector

frequency)

1-MHz Offset

–116

dBc/Hz

INTERNAL VCO SPECIFICATIONS

fVCO

VCO tuning range

2370

2600

MHz

Fine tuning sensitivity

fVCO at low end

16

(The range displayed in the typical

column indicates the lower sensitivity is

KVCO

MHz/V

typical at the lower end of the tuning

fVCO at high end

21

range, and the higher tuning sensitivity

is typical at the higher end of the tuning

range).

(12) A specification in modeling PLL in-band phase noise is the 1/f flicker noise, LPLL_flicker(f), which is dominant close to the carrier. Flicker

noise has a 10 dB/decade slope. PN10kHz is normalized to a 10 kHz offset and a 1 GHz carrier frequency. PN10kHz = LPLL_flicker(10

kHz) - 20log(Fout / 1 GHz), where LPLL_flicker(f) is the single side band phase noise of only the flicker noise's contribution to total noise,

L(f). To measure LPLL_flicker(f) it is important to be on the 10 dB/decade slope close to the carrier. A high compare frequency and a clean

crystal are important to isolating this noise source from the total phase noise, L(f). LPLL_flicker(f) can be masked by the reference

oscillator performance if a low power or noisy source is used. The total PLL in-band phase noise performance is the sum of LPLL_flicker(f)

and LPLL_flat(f).

(13) A specification modeling PLL in-band phase noise. The normalized phase noise contribution of the PLL, LPLL_flat(f), is defined as:

PN1HZ=LPLL_flat(f) - 20log(N) - 10log(fPD). LPLL_flat(f) is the single side band phase noise measured at an offset frequency, f, in a 1 Hz

bandwidth and fPD is the phase detector frequency of the synthesizer. LPLL_flat(f) contributes to the total noise, L(f).

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