SI53308 datasheet(1/32 Pages) SILABS

Part #	SI53308

Description	DUAL 1:3 LOW-JITTER BUFFER/LEVEL TRANSLATOR

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Manufacturer	SILABS [Silicon Laboratories]

Direct Link	http://www.silabs.com

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Rev. 0.9 6/13

Si53308

D UAL 1:3 L OW-J ITTER B UFFER/L EVEL TRANSLATOR

Features

Applications

Description

The Si53308 is an ultra low jitter six output differential buffer with pin-selectable

output clock signal format and divider selection. The device is a dual 1:3 buffer

providing the functionality of two independent buffers in a single IC. The Si53308

utilizes Silicon Laboratories' advanced CMOS technology to fanout clocks from 1

to 725 MHz with guaranteed low additive jitter, low skew, and low propagation

delay variability. The Si53308 features minimal cross-talk and provides superior

supply noise rejection, simplifying low jitter clock distribution in noisy

environments. Independent core and output bank supply pins provide integrated

level translation without the need for external circuitry.

Functional Block Diagram



6 differential or 12 (in phase)

LVCMOS outputs



Ultra-low additive jitter: 45 fs rms



Wide frequency range: 1 to 725 MHz



Any-format input with pin selectable

output formats: LVPECL, low power

LVPECL, LVDS, CML, HCSL,

LVCMOS



Synchronous output enable



Output clock division: /1, /2, /4



Low output-output skew: 25 ps



Loss of signal (LOS) monitors for

loss of input clock



Independent VDD and VDDO :

1.8/2.5/3.3 V



Selectable LVCMOS drive strength to

tailor jitter and EMI performance



Small size: 32-QFN (5 mm x 5 mm)



RoHS compliant, Pb-free



Industrial temperature range:

–40 to +85 °C



High-speed clock distribution



Ethernet switch/router



Optical Transport Network (OTN)



SONET/SDH



PCI Express Gen 1/2/3



Storage



Telecom



Industrial



Servers



Backplane clock distribution

VREF

DivA

DivB

Power

Supply

Filtering

Vref

Generator

VDDOB

OEB

SFOUTB[1:0]

Q0, Q1, Q2

OEA

VDDOA

SFOUTA[1:0]

DIVA

DIVB

CLK0

CLK1

Q3, Q4, Q5

Patents pending

Ordering Information:

See page 28.

Pin Assignments

GND

PAD

18

17

20

19

21

23

22

24

7

8

5

6

4

2

3

1

NC

VDD

Q0

Q5

VDDOA

VREF

GND

DIVA

SFOUTA[1]

SFOUTA[0]

DIVB

SFOUTB[1]

SFOUTB[0]

VDDOB

Si53308

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