SI53106 datasheet(11/34 Pages) SILABS

Part #	SI53106

Description	SIX-OUTPUT PCIE GEN 3 BUFFER/ZERO DELAY BUFFER

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Manufacturer	SILABS [Silicon Laboratories]

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Si53106

Rev. 1.2

11

Table 7. Clock Periods Differential Clock Outputs with SSC Disabled

SSC ON

Center

Freq, MHz

Measurement Window

Unit

1 Clock

1 µs

0.1s

1µs

1 Clock

–C–C

Jitter

AbsPer

Min

–SSC

Short

Term AVG

Min

–ppm

Long

Term AVG

Min

0ppm

Period

Nominal

+ppm

Long

Term AVG

Max

+SSC

Short

Term AVG

Max

+C–C

Jitter

AbsPer

Max

100.00

9.94900

9.99900

10.00000

10.00100

10.05100

ns

133.33

7.44925

7.49925

7.50000

7.50075

7.55075

ns

Table 8. Clock Periods Differential Clock Outputs with SSC Enabled

SSC ON

Center

Freq, MHz

Measurement Window

Unit

1 Clock

1 µs

0.1s

1µs

1 Clock

–C–C

Jitter

AbsPer

Min

–SSC

Short

Term AVG

Min

–ppm

Long

Term AVG

Min

0ppm

Period

Nominal

+ppm

Long

Term AVG

Max

+SSC

Short

Term AVG

Max

+C–C

Jitter

AbsPer

Max

99.75

9.94900

9.99900

10.02406

10.02506

10.02607

10.05126

10.10126

ns

133.33

7.44925

7.49925

7.51805

7.51880

7.51955

7.53845

7.58845

ns

Table 9. Absolute Maximum Ratings

Parameter

Symbol

Min

Max

Unit

3.3 V Core Supply Voltage1

VDD/VDD_A

—4.6

V

3.3 V I/O Supply Voltage1

VDD_IO

—4.6

V

3.3 V Input High Voltage1,2

VIH

—4.6

V

3.3 V Input Low Voltage1

VIL

−0.5

—

V

Storage Temperature1

ts

–65

150

°C

Input ESD protection3

ESD

2000

—

V

Notes:

1.

Consult manufacturer regarding extended operation in excess of normal dc operating parameters.

2.

Maximum VIH is not to exceed maximum VDD.

3.

Human body model.

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