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ADF5355BCPZ Datasheet(PDF) 10 Page - Analog Devices |
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ADF5355BCPZ Datasheet(HTML) 10 Page - Analog Devices |
10 / 38 page ADF5355 Data Sheet Pin No. Mnemonic Description 23 VREF Internal Compensation Node. DC biased at half the tuning range. Connect decoupling capacitors to the ground plane as close to this pin as possible. 24 VBIAS Reference Voltage. Connect a 100 nF decoupling capacitor to the ground plane as close to this pin as possible. 25, 32 CREG1, CREG2 Outputs from the LDO Regulator. Pin 25 and Pin 32 are the supply voltages to the digital circuits. Nominal voltage of 1.8 V. Decoupling capacitors of 100 nF connected to AGND are required for these pins. 26 PDBRF RFOUTA Power-Down. A logic low on this pin powers down the RFOUTA± outputs only. This power-down function is also software controllable. Do not leave this pin floating. 27 DVDD Digital Power Supply. This pin must be at the same voltage as AVDD. Place decoupling capacitors to the ground plane as close to this pin as possible. 28 REFINB Complementary Reference Input. If unused, ac couple this pin to AGND. 29 REFINA Reference Input. 30 MUXOUT Multiplexer Output. The multiplexer output allows the digital lock detect, the analog lock detect, scaled RF, or the scaled reference frequency to be externally accessible. 31 SDGND Digital Σ-Δ Modulator Ground. Pin 31 is the ground return path for the Σ-Δ modulator. EP Exposed Pad. The exposed pad must be connected to AGND. Rev. A | Page 10 of 38 |
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