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SI5380-EVB Datasheet(PDF) 1 Page - Silicon Laboratories |
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SI5380-EVB Datasheet(HTML) 1 Page - Silicon Laboratories |
1 / 50 page Ultra-Low Phase Noise, 12-output JESD204B Clock Generator Si5380 Data Sheet The Si5380 is a high performance, integer-based (M/N) clock generator for small cell ap- plications which demand the highest level of integration and phase noise performance. Based on Silicon Laboratories’ 4th generation DSPLL technology, the Si5380 combines frequency synthesis and jitter attenuation in a highly integrated digital solution that elimi- nates the need for external VCXO and loop filter components. A low cost, fixed-frequen- cy crystal provides frequency stability for free-run and holdover modes. This all-digital solution provides superior performance that is highly immune to external board distur- bances such as power supply noise. KEY FEATURES • Digital frequency synthesis eliminates external VCXO and analog loop filter components • Supports JESD204B clocking: DCLK and SYSREF • Input frequency range: • Differential: 10 MHz – 750 MHz • LVCMOS: 10 MHz – 250 MHz • Output frequency range: • Differential: 480 kHz – 1.47456 GHz • LVCMOS: 480 kHz – 250 MHz Applications • JESD204B clock generation • Remote Radio Units (RRU), Remote Access Networks (RAN), picocells, small cells • Wireless base stations (3G, GSM, W-CDMA, 4G/LTE, LTE-A) • Remote Radio Head (RRH), wireless repeaters, wireless backhaul • Data conversion sampling clocks (ADC, DAC, DDC, DUC) ÷P2 Si5380 54MHz XTAL XB XA OSC OUT7 OUT6 OUT5 OUT8 OUT1 OUT4 OUT3 OUT2 INTRb LOLb Status Monitor OUT0 OUT0A OUT9A OUT9 IN0 IN_SEL IN1 IN2 IN3/ FB_IN ÷N4 ÷N0 ÷N1 ÷N2 ÷N3 OEb SYNCb RSTb PDNb DSPLL ÷R1 ÷R2 ÷R3 ÷R4 ÷R5 ÷R6 ÷R7 ÷R8 ÷R9A ÷R9 ÷R0 ÷R0A I2C_SEL SDA/SDI A1/SDO SCLK A0/CSb NVM ÷P0 ÷P1 ÷P3 t4 t3 t2 t1 t0 I2C/ SPI silabs.com | Smart. Connected. Energy-friendly. Rev. 0.96 |
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