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SI5321-H-GL Datasheet(PDF) 1 Page - Silicon Laboratories |
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SI5321-H-GL Datasheet(HTML) 1 Page - Silicon Laboratories |
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1 / 34 page  Rev. 2.5 8/08 Copyright © 2008 by Silicon Laboratories Si5321 Si5321 SONET/SDH P RECISION C LOCK M ULTIPLIER IC Features Applications Description The Si5321 is a precision clock multiplier that exceeds the requirements of high-speed communication systems, including OC-192/OC-48 and 10 Gigabit Ethernet. This device phase locks to an input clock in the 19, 39, 78, 155, 311 or 622 MHz frequency range and generates a frequency-multiplied clock output that can be configured for operation in the 19, 39, 78, 155, 622, 1244, or 2488 MHz frequency range. Silicon Laboratories DSPLL® technology provides PLL functionality with unparalleled performance. It eliminates external loop filter components, provides programmable loop parameters, and simplifies design. FEC rates are supported by selectable forward and reverse 255/ 238 (15/14), 255/237 (85/79), and 66/64 (33/32) conversion factors. The ITU-T G.709 255/237 rate and the IEEE 802.3ae 66/64 rate are supported when using a 155 MHz or higher rate input clock. The performance and integration of Silicon Laboratories’ Si5321 clock IC provides high-level support of the latest specifications and systems. It operates from a single 3.3 V supply. Functional Block Diagram Ultra-low jitter clock output with jitter generation as low as 0.3 psRMS No external components (other than a resistor and bypassing) Input clock ranges at 19, 39, 78, 155, 311, or 622 MHz Output clock ranges at 19, 39, 78, 155, 311, 622, 1244, or 2488 MHz Maximum range includes 693 MHz for 10 GbE FEC support Digital hold for loss-of-input clock Support for 255/238 (15/14), 255/237 (85/79), and 66/64 FEC scaling (ITU-T G.709 and IEEE 802.3ae) Selectable loop bandwidth Loss-of-signal alarm output Low power Small size (9 x 9 mm) Backwards compatible with Si5320 SONET/SDH line/port cards Terabit routers Core switches Digital cross connects INFRQSEL[2:0] FRQSEL[2:0] CLKOUT+ CLKOUT– 2 CAL_ACTV 2 FEC[2:0] BWSEL[1:0] 3 2 Biasing & Supply Regulation REXT VSEL33 VDD GND ÷ DH_ACTV ÷ Signal Detect Calibration RSTN/CAL 2 CLKIN+ CLKIN– VALTIME LOS FXDDELAY BWBOOST DSPLL ® Ordering Information: See page 30. Si5321 Si5321 |
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