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LMK04816BISQX Datasheet(PDF) 1 Page - Texas Instruments |
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LMK04816BISQX Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 129 page  FPGA DAC LMX2541 PLL+VCO Recovered ³GLUW\´ FORFN RU clean clock 0XOWLSOH ³FOHDQ´ clocks at different frequencies CLKout4, 5, 6, 7 CLKout2 CLKout0, 1 FPGA CLKin0 Crystal or VCXO Backup Reference Clock CLKin2 OSCout0 CLKout11 CLKout8A DAC CLKout9 IF I Q ADC Serializer/ Deserializer CPLD LMK04816 Precision Clock Conditioner CLKout3 CLKin1 Product Folder Sample & Buy Technical Documents Tools & Software Support & Community LMK04816 SNAS597C – JULY 2012 – REVISED JANUARY 2016 LMK04816 Three Input Low-Noise Clock Jitter Cleaner With Dual Loop PLLs 1 Features 2 Applications 1 • Ultralow RMS Jitter Performance • Data Converter Clocking and Wireless Infrastructure – 100-fs RMS Jitter (12 kHz to 20 MHz) • Networking, SONET or SDH, DSLAM – 123-fs RMS Jitter (100 Hz to 20 MHz) • Medical, Video, Military, and Aerospace • Dual-Loop PLLATINUM™ PLL Architecture • Test and Measurement – PLL1 – Integrated Low-Noise Crystal Oscillator 3 Description Circuit The LMK04816 device is the industry's highest – Holdover Mode When Input Clocks are Lost performance clock conditioner with superior clock – Automatic or Manual Triggering and jitter cleaning, generation, and distribution with Recovery advanced features to meet next generation system requirements. The dual-loop PLLATINUM architecture – PLL2 enables 111-fs RMS jitter (12 kHz to – Normalized 1-Hz PLL Noise Floor of 20 MHz) using a low-noise VCXO module or sub- –227 dBc/Hz 200-fs RMS jitter (12 kHz to 20 MHz) using a low- cost external crystal and varactor diode. – Phase Detector Rate Up to 155 MHz – OSCin Frequency-Doubler The dual-loop architecture consists of two high- performance phase-locked loops (PLL), a low-noise – Integrated Low-Noise VCO crystal oscillator circuit, and a high-performance – VCO Frequency Ranges From 2370 MHz voltage controlled oscillator (VCO). The first PLL to 2600 MHz (PLL1) provides a low-noise jitter cleaner function • Three Redundant Input Clocks With LOS while the second PLL (PLL2) performs the clock generation. PLL1 can be configured to either work – Automatic and Manual Switch-Over Modes with an external VCXO module or the integrated • 50% Duty Cycle Output Divides, 1 to 1045 (Even crystal oscillator with an external tunable crystal and and Odd) varactor diode. When used with a very narrow loop • LVPECL, LVDS, or LVCMOS Programmable bandwidth, PLL1 uses the superior close-in phase Outputs noise (offsets below 50 kHz) of the VCXO module or the tunable crystal to clean the input clock. The • Precision Digital Delay, Fixed or Dynamically- output of PLL1 is used as the clean input reference to Adjustable PLL2 where it locks the integrated VCO. The loop • 25-ps Step Analog Delay Control, Up to 575 ps bandwidth of PLL2 can be optimized to clean the far- • 1/2 Clock Distribution Period Step Digital Delay, out phase noise (offsets above 50 kHz) where the integrated VCO outperforms the VCXO module or up to 522 Steps tunable crystal used in PLL1. • 13 Differential Outputs; up to 26 Single-Ended – Up to 5 VCXO and Crystal-Buffered Outputs Device Information(1) • Clock Rates of Up to 2600 MHz PART NUMBER PACKAGE BODY SIZE (NOM) • 0-Delay Mode LMK04816 WQFN (64) 9.00 mm × 9.00 mm • Three Default Clock Outputs at Power Up (1) For all available packages, see the orderable addendum at the end of the data sheet. • Multi-Mode: Dual PLL, Single PLL, and Clock Distribution Simplified Schematic • Industrial Temperature Range: –40°C to +85°C • 3.15-V to 3.45-V Operation • Package: 64-Pin WQFN (9.0 × 9.0 × 0.8 mm) 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. |
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