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LMK04816BISQX Datasheet(PDF) 9 Page - Texas Instruments |
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LMK04816BISQX Datasheet(HTML) 9 Page - Texas Instruments |
9 / 129 page LMK04816 www.ti.com SNAS597C – JULY 2012 – REVISED JANUARY 2016 Electrical Characteristics (continued) 3.15 V ≤ VCC ≤ 3.45 V, –40°C ≤ TA ≤ 85°C. Typical values represent most likely parametric norms at VCC = 3.3 V, TA = 25°C, at the Recommended Operating Conditions at the time of product characterization and are not ensured. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PLL 1/f noise at 10-kHz PLL2_CP_GAIN = 400 µA –118 offset (10) PN10kHz dBc/Hz Normalized to 1-GHz PLL2_CP_GAIN = 3200 µA –121 output frequency PLL2_CP_GAIN = 400 µA –222.5 Normalized phase noise PN1Hz dBc/Hz contribution (11) PLL2_CP_GAIN = 3200 µA –227 INTERNAL VCO SPECIFICATIONS fVCO VCO tuning range LMK04816 2370 2600 MHz lower end of the tuning range 16 KVCO Fine tuning sensitivity LMK04816 MHz/V higher end of the tuning range 21 Allowable temperature After programming R30 for lock, no changes to | ΔTCL| drift for continuous lock output configuration are permitted to ensure 125 °C (12) (3) continuous lock CLKOUT CLOSED-LOOP JITTER SPECIFICATIONS USING A COMMERCIAL QUALITY VCXO(13) Offset = 1 kHz –122.5 LMK04816 Offset = 10 kHz –132.9 fCLKout = 245.76 MHz Offset = 100 kHz –135.2 SSB phase noise L(f)CLKout Measured at clock Offset = 800 kHz –143.9 dBc/Hz outputs Offset = 10 MHz; LVDS –156 Value is average for all Offset = 10 MHz; LVPECL 1600 mVpp –157.5 output types (14) Offset = 10 MHz; LVCMOS –157.1 JCLKout LMK04816(14) BW = 12 kHz to 20 MHz 115 LVDS/LVPECL/L fCLKout = 245.76 MHz fs rms BW = 100 Hz to 20 MHz 123 VCMOS Integrated RMS jitter CLKOUT CLOSED-LOOP JITTER SPECIFICATIONS USING THE INTEGRATED LOW-NOISE CRYSTAL OSCILLATOR CIRCUIT(15) BW = 12 kHz to 20 MHz 192 LMK04816 XTAL_LVL = 3 fCLKout = 245.76 MHz fs rms BW = 100 Hz to 20 MHz Integrated RMS jitter 450 XTAL_LVL = 3 DEFAULT POWER ON RESET CLOCK OUTPUT FREQUENCY Default output clock fCLKout-startup frequency at device CLKout8, LVDS, LMK04816 90 98 110 MHz power-on (16) (10) A specification in modeling PLL in-band phase noise is the 1/f flicker noise, LPLL_flicker(f), which is dominant close to the carrier. Flicker noise has a 10 dB/decade slope. PN10kHz is normalized to a 10 kHz offset and a 1 GHz carrier frequency. PN10kHz = LPLL_flicker(10 kHz) - 20log(Fout / 1 GHz), where LPLL_flicker(f) is the single side band phase noise of only the flicker noise's contribution to total noise, L(f). To measure LPLL_flicker(f) it is important to be on the 10-dB/decade slope close to the carrier. A high compare frequency and a clean crystal are important to isolating this noise source from the total phase noise, L(f). LPLL_flicker(f) can be masked by the reference oscillator performance if a low power or noisy source is used. The total PLL in-band phase noise performance is the sum of LPLL_flicker(f) and LPLL_flat(f). (11) A specification modeling PLL in-band phase noise. The normalized phase noise contribution of the PLL, LPLL_flat(f), is defined as: PN1HZ=LPLL_flat(f) - 20log(N) - 10log(fPDX). LPLL_flat(f) is the single side band phase noise measured at an offset frequency, f, in a 1 Hz bandwidth and fPDX is the phase detector frequency of the synthesizer. LPLL_flat(f) contributes to the total noise, L(f). (12) Maximum Allowable Temperature Drift for Continuous Lock is how far the temperature can drift in either direction from the value it was at the time that the R30 register was last programmed, and still have the part stay in lock. The action of programming the R30 register, even to the same value, activates a frequency calibration routine. This implies the part works over the entire frequency range, but if the temperature drifts more than the maximum allowable drift for continuous lock, then it is necessary to reload the R30 register to ensure it stays in lock. Regardless of what temperature the part was initially programmed at, the temperature can never drift outside the frequency range of –40°C to 85°C without violating specifications. (13) VCXO used is a 122.88 MHz Crystek CVHD-950-122.880. (14) fVCO = 2457.6 MHz, PLL1 parameters: EN_PLL2_REF_2X = 1, PLL2_R = 2, FPD1 = 1.024 MHz, ICP1 = 100 μA, loop bandwidth = 10 Hz. A 122.88 MHz Crystek CVHD-950–122.880. PLL2 parameters: PLL2_R = 1, FPD2 = 122.88 MHz, ICP2 = 3200 μA, C1 = 47 pF, C2 = 3.9 nF, R2 = 620 Ω, PLL2_C3_LF = 0, PLL2_R3_LF = 0, PLL2_C4_LF = 0, PLL2_R4_LF = 0, CLKoutX_Y_DIV = 10, and CLKoutX_ADLY_SEL = 0. (15) Crystal used is a 20.48 MHz Vectron VXB1-1150-20M480 and Skyworks varactor diode, SMV-1249-074LF. (16) CLKout6 and OSCout0 also oscillate at start-up at the frequency of the VCXO attached to OSCin port. Copyright © 2012–2016, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: LMK04816 |
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