LMK03318RHSR datasheet(2/136 Pages) TI1

Part #	LMK03318RHSR

Description	Ultra-Low-Noise Jitter Clock Generator Family

Download	136 Pages

Scroll/Zoom	100%

Manufacturer	TI1 [Texas Instruments]

Direct Link	http://www.ti.com

Logo

2 / 136 page

LMK03318

SNAS669A – SEPTEMBER 2015 – REVISED DECEMBER 2015

www.ti.com

4 Description Continued

For the PLL, a differential/single-ended clock or crystal input can be selected as its reference clock. The selected

reference input can be used to lock the VCO frequency at an integer or fractional multiple of the reference input

frequency. The VCO frequency can be tuned between 4.8 GHz and 5.4 GHz. The PLL offers the flexibility to

select a predefined or user-defined loop bandwidth, depending on the needs of the application. The PLL has a

post-divider that can be selected between divide-by 2, 3, 4, 5, 6, 7 or 8.

All the output channels can select the divided-down VCO clock from the PLL as the source for the output divider

to set the final output frequency. Some output channels can also independently select the reference input for the

PLL as an alternative source to be bypassed to the corresponding output buffers. The 8-bit output dividers

support a divide range of 1 to 256 (even or odd), output frequencies up to 1 GHz, and output phase

synchronization capability.

All output pairs are ground-referenced CML drivers with programmable swing that can be interfaced to LVDS,

LVPECL or CML receivers with AC coupling. All output pairs can also be independently configured as HCSL

outputs or 2 × 1.8-V LVCMOS outputs. The outputs offer lower power at 1.8 V, higher performance and power

supply noise immunity, and lower EMI compared to voltage-referenced driver designs (such as traditional LVDS

and LVPECL drivers). Two additional 3.3-V LVCMOS outputs can be obtained via the STATUS pins. This is an

optional feature in case of a need for 3.3-V LVCMOS outputs and device status signals are not needed.

The device features self start-up from on-chip programmable EEPROM or pre-defined ROM memory, which

offers multiple custom device modes selectable via pin control eliminating the need for serial programming. The

device registers and on-chip EEPROM settings are fully programmable via the I2C-compatible serial interface.

The device slave address is programmable in EEPROM and LSBs can be set with a 3-state pin.

The device provides two frequency margining options with glitch-free operation to support system design

verification tests (DVT), such as standard compliance and system timing margin testing. Fine frequency

margining (in ppm) can be supported by using a low-cost pullable crystal on the internal crystal oscillator (XO),

and selecting this input as the reference to the PLL synthesizer. The frequency margining range is determined by

the crystal’s trim sensitivity and the on-chip varactor range. XO frequency margining can be controlled through

pin or I2C control for ease-of use and high flexibility. Coarse frequency margining (in %) is available on any

output channel by changing the output divide value via I2C interface, which synchronously stops and restarts the

output clock to prevent a glitch or runt pulse when the divider is changed.

Internal power conditioning provide excellent power supply ripple rejection (PSRR), reducing the cost and

complexity of the power delivery network. The analog and digital core blocks operate from 3.3 V ± 5% supply and

output blocks operate from 1.8 V, 2.5 V, or 3.3 V ± 5% supply.

5 Device Comparison Table

Table 1. LVPECL Output Jitter over Different Integration Bandwidths

OUTPUT FREQUENCY (MHz)

INTEGRATION BANDWIDTH

TYPICAL JITTER (ps, rms)

< 100

12 kHz - 5 MHz

0.15

> 100

1 kHz – 5 MHz

0.1

12 kHz – 20 MHz

6 Revision History

Changes from Original (September 2015) to Revision A

Page

•

Product Preview to Production Data full release ................................................................................................................... 1

2

Submit Documentation Feedback

Product Folder Links: LMK03318

Similar Part No. - LMK03318RHSR

Manufacturer	Part #	Datasheet	Description
Texas Instruments	LMK03328	2Mb / 153P	[Old version datasheet] Ultra-Low Jitter Clock Generator
	LMK03328EVM	6Mb / 56P	[Old version datasheet] LMK03328EVM User?셲 Guide
	LMK03328RHSR	2Mb / 153P	[Old version datasheet] Ultra-Low Jitter Clock Generator
	LMK03328RHST	2Mb / 153P	[Old version datasheet] Ultra-Low Jitter Clock Generator

More results

Similar Description - LMK03318RHSR

Manufacturer	Part #	Datasheet	Description
Texas Instruments	LMK03328	2Mb / 153P	[Old version datasheet] Ultra-Low Jitter Clock Generator
Pericom Semiconductor C...	PI6CXG06F62A	580Kb / 2P	FlexOut Ultra Low Jitter Clock Generator
Integrated Device Techn...	8V41NS0412	1Mb / 51P	NG Ultra Low Jitter HCSL Clock Generator
Analog Devices	AD9523-1	1Mb / 63P	Low Jitter Clock Generator
Analog Devices	AD9523-1BCPZ	840Kb / 60P	Low Jitter Clock Generator REV. B
ON Semiconductor	P1P8160A	129Kb / 6P	Low Jitter Clock Generator October, 2010 ??Rev. 2
Texas Instruments	LMK04906	1Mb / 113P	[Old version datasheet] Ultra Low Noise Clock Jitter Cleaner/Multiplier
	LMK04000	1Mb / 66P	[Old version datasheet] Family Low-Noise Clock Jitter Cleaner with Cascaded PLLs
	LMK04821	2Mb / 113P	[Old version datasheet] Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner
	LMK04828-EP	2Mb / 102P	[Old version datasheet] Ultra-Low-Noise, JESD204B-Compliant Clock Jitter Cleaner

More results

LMK03318RHSR Datasheet(PDF) 2 Page - Texas Instruments

LMK03318RHSR Datasheet(HTML) 2 Page - Texas Instruments

Similar Part No. - LMK03318RHSR

Similar Description - LMK03318RHSR

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL