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SI598 Datasheet(PDF) 9 Page - Silicon Laboratories |
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SI598 Datasheet(HTML) 9 Page - Silicon Laboratories |
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9 / 28 page  Si598/Si599 Rev. 1.0 9 Table 7. CLK± Output Period Jitter (Typical values TA = 25 ºC, VDD = 3.3 V unless otherwise noted) Parameter Symbol Test Condition Min Typ Max Units Period Jitter* JPER RMS — 3 — ps Peak-to-Peak — 35 — ps *Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Table 8. CLK± Output Phase Noise (Typical, Si599) (Typical values TA = 25 ºC, VDD =3.3 V) Offset Frequency 74.25 MHz 185 ppm/V LVPECL 148.5 MHz 185 ppm/V LVPECL 155.52 MHz 95 ppm/V LVPECL Units 100 Hz 1kHz 10 kHz 100 kHz 1MHz 10 MHz 20 MHz –77 –101 –121 –134 –149 –151 –150 –68 –95 –116 –128 –144 –147 –148 –77 –101 –119 –127 –144 –147 –148 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz Table 9. Power Supply Noise Rejection (Typical values TA = 25 ºC, VDD =3.3 V) Parameter Symbol Test Condition Min Typ Max Units RMS Additive Jitter due to Power Supply Noise* φPSRR 100 kHz — 0.32 — ps 300 kHz — 0.36 — ps 700 kHz — 0.36 — ps 1MHz — 0.32 — ps *Note: Measured with 100 mVp-p sinusoid applied to power supply pin. VDD = 3.3 V, LVPECL. Table 10. Spurious Performance (Typical values TA = 25 ºC, VDD =3.3 V) Parameter Symbol Test Condition Min Typ Max Units Spurious Free Dynamic Range SFDR LVPECL, LVDS, CML1 —75 — dB LVPECL, LVDS, CML2 —64 — dB CMOS1 —77 — dB Notes: 1. 10 to 160 MHz. 2. 10 to 810 MHz. |
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