EFM32WG295F128-BGA120 datasheet(4/82 Pages) SILABS

Part #	EFM32WG295F128-BGA120

Description	Output state retention and wake-up from Shutoff Mode

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2014-06-13 - EFM32WG295FXX - d0189_Rev1.40

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2.1.3 Memory System Controller (MSC)

The Memory System Controller (MSC) is the program memory unit of the EFM32WG microcontroller.

The flash memory is readable and writable from both the Cortex-M4 and DMA. The flash memory is

divided into two blocks; the main block and the information block. Program code is normally written to

the main block. Additionally, the information block is available for special user data and flash lock bits.

There is also a read-only page in the information block containing system and device calibration data.

Read and write operations are supported in the energy modes EM0 and EM1.

2.1.4 Direct Memory Access Controller (DMA)

The Direct Memory Access (DMA) controller performs memory operations independently of the CPU.

This has the benefit of reducing the energy consumption and the workload of the CPU, and enables

the system to stay in low energy modes when moving for instance data from the USART to RAM or

from the External Bus Interface to a PWM-generating timer. The DMA controller uses the PL230 µDMA

controller licensed from ARM.

2.1.5 Reset Management Unit (RMU)

The RMU is responsible for handling the reset functionality of the EFM32WG.

2.1.6 Energy Management Unit (EMU)

The Energy Management Unit (EMU) manage all the low energy modes (EM) in EFM32WG microcon-

trollers. Each energy mode manages if the CPU and the various peripherals are available. The EMU

can also be used to turn off the power to unused SRAM blocks.

2.1.7 Clock Management Unit (CMU)

The Clock Management Unit (CMU) is responsible for controlling the oscillators and clocks on-board the

EFM32WG. The CMU provides the capability to turn on and off the clock on an individual basis to all

peripheral modules in addition to enable/disable and configure the available oscillators. The high degree

of flexibility enables software to minimize energy consumption in any specific application by not wasting

power on peripherals and oscillators that are inactive.

2.1.8 Watchdog (WDOG)

The purpose of the watchdog timer is to generate a reset in case of a system failure, to increase appli-

cation reliability. The failure may e.g. be caused by an external event, such as an ESD pulse, or by a

software failure.

2.1.9 Peripheral Reflex System (PRS)

The Peripheral Reflex System (PRS) system is a network which lets the different peripheral module

communicate directly with each other without involving the CPU. Peripheral modules which send out

Reflex signals are called producers. The PRS routes these reflex signals to consumer peripherals which

apply actions depending on the data received. The format for the Reflex signals is not given, but edge

triggers and other functionality can be applied by the PRS.

2.1.10 External Bus Interface (EBI)

The External Bus Interface provides access to external parallel interface devices such as SRAM, FLASH,

ADCs and LCDs. The interface is memory mapped into the address bus of the Cortex-M4. This enables

seamless access from software without manually manipulating the IO settings each time a read or write

is performed. The data and address lines are multiplexed in order to reduce the number of pins required

to interface the external devices. The timing is adjustable to meet specifications of the external devices.

The interface is limited to asynchronous devices.

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EFM32WG295F128-BGA120 Datasheet(PDF) 4 Page - Silicon Laboratories

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