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EFM32WG290F256-BGA112 Datasheet(PDF) 7 Page - Silicon Laboratories |
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EFM32WG290F256-BGA112 Datasheet(HTML) 7 Page - Silicon Laboratories |
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7 / 82 page  ...the world's most energy friendly microcontrollers 2014-06-13 - EFM32WG290FXX - d0188_Rev1.40 7 www.silabs.com 2.1.27 Low Energy Sensor Interface (LESENSE) The Low Energy Sensor Interface (LESENSE TM), is a highly configurable sensor interface with support for up to 16 individually configurable sensors. By controlling the analog comparators and DAC, LESENSE is capable of supporting a wide range of sensors and measurement schemes, and can for instance mea- sure LC sensors, resistive sensors and capacitive sensors. LESENSE also includes a programmable FSM which enables simple processing of measurement results without CPU intervention. LESENSE is available in energy mode EM2, in addition to EM0 and EM1, making it ideal for sensor monitoring in applications with a strict energy budget. 2.1.28 Backup Power Domain The backup power domain is a separate power domain containing a Backup Real Time Counter, BURTC, and a set of retention registers, available in all energy modes. This power domain can be configured to automatically change power source to a backup battery when the main power drains out. The backup power domain enables the EFM32WG290 to keep track of time and retain data, even if the main power source should drain out. 2.1.29 Advanced Encryption Standard Accelerator (AES) The AES accelerator performs AES encryption and decryption with 128-bit or 256-bit keys. Encrypting or decrypting one 128-bit data block takes 52 HFCORECLK cycles with 128-bit keys and 75 HFCORECLK cycles with 256-bit keys. The AES module is an AHB slave which enables efficient access to the data and key registers. All write accesses to the AES module must be 32-bit operations, i.e. 8- or 16-bit operations are not supported. 2.1.30 General Purpose Input/Output (GPIO) In the EFM32WG290, there are 90 General Purpose Input/Output (GPIO) pins, which are divided into ports with up to 16 pins each. These pins can individually be configured as either an output or input. More advanced configurations like open-drain, filtering and drive strength can also be configured individually for the pins. The GPIO pins can also be overridden by peripheral pin connections, like Timer PWM outputs or USART communication, which can be routed to several locations on the device. The GPIO supports up to 16 asynchronous external pin interrupts, which enables interrupts from any pin on the device. Also, the input value of a pin can be routed through the Peripheral Reflex System to other peripherals. 2.2 Configuration Summary The features of the EFM32WG290 is a subset of the feature set described in the EFM32WG Reference Manual. Table 2.1 (p. 7) describes device specific implementation of the features. Table 2.1. Configuration Summary Module Configuration Pin Connections Cortex-M4 Full configuration NA DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO MSC Full configuration NA DMA Full configuration NA RMU Full configuration NA EMU Full configuration NA CMU Full configuration CMU_OUT0, CMU_OUT1 WDOG Full configuration NA |
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