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XC167CI Datasheet(PDF) 9 Page - Infineon Technologies AG |
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XC167CI Datasheet(HTML) 9 Page - Infineon Technologies AG |
9 / 80 page XC167 Derivatives General Device Information Data Sheet 5 V1.1, 2003-06 Preliminary 2.2 Pin Configuration and Definition The pins of the XC167 are described in detail in Table 2, including all their alternate functions. Figure 2 summarizes all pins in a condensed way, showing their location on the 4 sides of the package. E*) and C*) mark pins to be used as alternate external interrupt inputs, C*) marks pins that can have CAN interface lines assigned to them. Figure 2 Pin Configuration (top view) 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 NC NC P20.12/RSTOUT NMI VSSP VDDP P6.0/CS0/CC0IO P6.1/CS1/CC1IO P6.2/CS2/CC2IO P6.3/CS3/CC3IO P6.4/CS4/CC4IO P6.5/HOLD/CC5IO P6.6/HLDA/CC6IO P6.7/BREQ/CC7IO P7.4/CC28IO/C*) P7.5/CC29IO/C*) P7.6/CC30IO/C*) P7.7/CC31IO/C*) VSSP VDDP P9.0/SDA0/CC16Io/C*) P9.1/SCL0/CC17Io/C*) P9.2/SDA1/CC18Io/C*) P9.3/SCL1/CC19Io/C*) P9.4/SDA2/CC20IO P9.5/SCL2/CC21IO VSSP VDDP P5.0/AN0 P5.1/AN1 P5.2/AN2 P5.3/AN3 P5.4/AN4 P5.5/AN5 P5.10/AN10/T6EUD P5.11/AN11/T5EUD XC167 NC NC P0H.1/AD9 P0H.0/AD8 VSSP VDDP P0L.7/AD7 P0L.6/AD6 P0L.5/AD5 P0L.4/AD4 P0L.3/AD3 P0L.2/AD2 P0L.1/AD1 P0L.0/AD0 P20.5/EA P20.4/ALE P20.2/READY P20.1/WR/WRL P20.0/RD VSSP VDDP P4.7/A23/C*) P4.6/A22/C*) P4.5/A21/C*) P4.4/A20/C*) P4.3/A19 P4.2/A18 P4.1/A17 P4.0/A16 VSSI VDDI P3.15/CLKOUT/FO P3.13/SCLK0/E*) P3.12/BHE/WRH/ TMS /E*) TDO |
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