EFM8SB10F4G-A-QFN20 datasheet(9/55 Pages) SILABS

Part #	EFM8SB10F4G-A-QFN20

Description	The EFM8SB1 highlighted features are listed below

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Manufacturer	SILABS [Silicon Laboratories]

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12-Bit Analog-to-Digital Converter (ADC0)

The ADC is a successive-approximation-register (SAR) ADC with 12-, 10-, and 8-bit modes, integrated track-and hold and a program-

mable window detector. The ADC is fully configurable under software control via several registers. The ADC may be configured to

measure different signals using the analog multiplexer. The voltage reference for the ADC is selectable between internal and external

reference sources.

• Up to 10 external inputs.

• Single-ended 12-bit and 10-bit modes.

• Supports an output update rate of 75 ksps samples per second in 12-bit mode or 300 ksps samples per second in 10-bit mode.

• Operation in low power modes at lower conversion speeds.

• Asynchronous hardware conversion trigger, selectable between software, external I/O and internal timer sources.

• Output data window comparator allows automatic range checking.

• Support for burst mode, which produces one set of accumulated data per conversion-start trigger with programmable power-on set-

tling and tracking time.

• Conversion complete and window compare interrupts supported.

• Flexible output data formatting.

• Includes an internal 1.65 V fast-settling reference and support for external reference.

• Integrated temperature sensor.

Low Current Comparator (CMP0)

An analog comparator is used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is higher.

External input connections to device I/O pins and internal connections are available through separate multiplexers on the positive and

negative inputs. Hysteresis, response time, and current consumption may be programmed to suit the specific needs of the application.

The comparator module includes the following features:

• Input options in addition to the pins:

• Capacitive Sense Comparator output.

• VDD.

• VDD divided by 2.

• Internal connection to LDO output.

• Direct connection to GND.

• Synchronous and asynchronous outputs can be routed to pins via crossbar.

• Programmable hysteresis between 0 and ±20 mV.

• Programmable response time.

• Interrupts generated on rising, falling, or both edges.

EFM8SB1 Data Sheet

System Overview

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Rev. 1.2 | 8

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EFM8SB10F4G-A-QFN20 Datasheet(PDF) 9 Page - Silicon Laboratories

EFM8SB10F4G-A-QFN20 Datasheet(HTML) 9 Page - Silicon Laboratories

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