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C8051F965-B-GM Datasheet(PDF) 1 Page - Silicon Laboratories |
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C8051F965-B-GM Datasheet(HTML) 1 Page - Silicon Laboratories |
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1 / 492 page  Ultra Low Power 128K, LCD MCU Family C8051F96x Rev. 1.0 7/13 Copyright © 2013 by Silicon Laboratories C8051F96x Ultra Low Power Consumption at 3.6 V - 130 µA/MHz Low-Power Active mode with dc-dc enabled - 120 nA sleep current w/ data retention; POR monitor enabled - 450 nA sleep mode with SmaRTClock (internal LFO) - 600 nA sleep mode with SmaRTClock (ext. crystal) - 2 µs wakeup time; 1.5 µA analog settling time 12-Bit; 16 Ch. Analog-to-Digital Converter - Up to 75 ksps (12-bit mode) or 300 ksps (10-bit mode) - External pin or internal VREF (no ext cap required) - On-chip voltage reference; 0.5x gain allows measur- ing voltages up to twice the reference voltage - Autonomous burst mode with 16-bit auto-averaging accumulator - Integrated temperature sensor Two Low Current Comparators - Programmable hysteresis and response time - Configurable as wake-up or reset source Internal 6-Bit Current Reference - Up to ±500 µA; source and sink capability - Enhanced resolution via PWM interpolation Integrated LCD Controller - Supports up to 128 segments (32x4) - LCD controller consumes only 400 nA for 32-segment static display - Integrated charge pump for contrast control Metering-Specific Peripherals - DC-DC buck converter allows dynamic voltage scaling for maximum efficiency (250 mW output) - Sleep-mode pulse accumulator with programmable switch, de-bounce and pull-up control; interfaces directly to metering sensor - Data Packet Processing Engine (DPPE) includes hardware AES, DMA, CRC and encoding blocks for acceleration of wireless protocols High-Speed 8051 µC Core - Pipelined instruction architecture; executes 70% of instructions in 1 or 2 system clocks Memory - Up to 128 kB Flash; In-system programmable; Full read/write/erase functionality over supply range - Up to 8 kB internal data RAM Digital Peripherals - 57 or 34 port I/O; All 5 V tolerant with high sink current and programmable drive strength - Hardware SMBus™ (I2C™ Compatible), 2 x SPI™, and UART serial ports available concurrently - Four general purpose 16-bit counter/timers - Programmable 16-bit counter/timer array with six capture/compare modules and watchdog timer Clock Sources - Precision Internal oscillator: 24.5 MHz, 2% accuracy supports UART operation; spread-spectrum mode for reduced EMI - Low power internal oscillator: 20 MHz - External oscillator: Crystal, RC, C, or CMOS Clock - SmaRTClock oscillator: 32 kHz Crystal or 16.4 kHz internal LFO On-Chip Debug - On-chip debug circuitry facilitates full-speed, non- intrusive in-system debug (no emulator required) - Provides 4 breakpoints, single stepping Packages - 76-pin DQFN (6 x 6 mm) - 40-pin QFN (6 x 6 mm) - 80-pin TQFP (12 x 12 mm) Temperature Range: –40 to +85 °C Port 0 Drivers Digital Peripherals UART Timers 0, 1, 2, 3 PCA/WDT SMBus Priority Crossbar Decoder P0.0/VREF P0.1/AGND P0.2/XTAL1 P0.3/XTAL2 P0.4/TX P0.5/RX P0.6/CNVSTR P0.7 Crossbar Control Port I/O Configuration CIP-51 8051 Controller Core 128k Byte ISP Flash Program Memory 256 Byte SRAM SFR Bus 8092 Byte XRAM Port 1 Drivers P1.0/PC0 P1.1/PC1 P1.2/XTAL3 P1.3/XTAL4 P1.4 P1.5/INT5 Port 2 Drivers P2.0/SCK1 P2.1/MISO1 P2.2/MOSI1 P2.3/NSS1 P2.4 SPI 0 Analog Peripherals Comparators + - VBAT VBAT VDC XTAL1 SYSCLK System Clock Configuration External Oscillator Circuit Precision 24.5 MHz Oscillator Debug / Programming Hardware Power On Reset/PMU Reset C2D C2CK/RST Wake 12-bit 75ksps ADC A M U X Temp Sensor External VREF Internal VREF VDD XTAL2 Low Power 20 MHz Oscillator VREF GND P1.6/INT6 P1.7 CP0, CP0A P2.5 P2.6 P2.7 + - CP1, CP1A Enhanced smaRTClock Oscillator XTAL3 XTAL4 DC/DC Buck Converter IND GNDDC VREG Digital Power CRC Engine P3-6 Drivers P7 Driver LCD Charge Pump AES Engine DMA CAP P3.0...P6.7 P7.0/C2D 16 32 Pulse Counter LCD (up to 4x32) Encoder EMIF GND VDD Analog Power SPI 1 (DMA Enabled) VBATDC |
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