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TLV320AIC3104IRHBR Datasheet(PDF) 10 Page - Texas Instruments |
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TLV320AIC3104IRHBR Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 95 page  TLV320AIC3104 SLAS510D – FEBRUARY 2007 – REVISED DECEMBER 2014 www.ti.com Electrical Characteristics (continued) At 25°C, AVDD = DRVDD = IOVDD = 3.3 V, DVDD = 1.8 V, fS = 48 kHz, 16-bit audio data (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Power supply rejection ratio 217 Hz, 100 mVpp on AVDD, DRVDD1/2 48 dB Mute attenuation 1-kHz output 107 dB DIGITAL I/O 0.3 VIL Input low level –0.3 V IOVDD 0.7 IOVDD > 1.6 V IOVDD VIH Input high level (5) V IOVDD ≤ 1.6 V 1.1 0.1 VOL Output low level V IOVDD 0.8 VOH Output high level V IOVDD CURRENT CONSUMPTION – DRVDD = AVDD = IOVDD = 3.3 V, DVDD = 1.8 V IDRVDD + IAVDD 0.1 RESET held low μA IDVDD 0.2 IDRVDD + IAVDD 2.15 Mono ADC record, fS = 8 ksps, I2S slave, AGC off, no signal IDVDD 0.48 IDRVDD + IAVDD 4.1 Stereo ADC record, fS = 8 ksps, I2S slave, AGC off, no signal IDVDD 0.62 IDRVDD + IAVDD 4.31(6) Stereo ADC record, fS = 48 ksps, I2S slave, AGC off, no signal IDVDD 2.45(6) IDRVDD + IAVDD 3.5 Stereo DAC playback to lineout, analog mixer bypassed, fS = 48 ksps, I2S slave IDVDD 2.3 IIN mA IDRVDD + IAVDD 4.9 Stereo DAC playback to lineout, fS = 48 ksps, I2S slave, no signal IDVDD 2.3 IDRVDD + IAVDD 6.7 Stereo DAC playback to stereo single-ended headphone, fS = 48 ksps, I2S slave, no signal IDVDD 2.3 IDRVDD + IAVDD 3.11 Stereo line in to stereo line out, no signal IDVDD 0 IDRVDD + IAVDD 1.4 Extra power when PLL enabled IDVDD 0.9 IDRVDD + IAVDD 28 All blocks powered down. Headset detection μA enabled, headset not inserted IDVDD 2 (5) When IOVDD < 1.6 V, minimum VIH is 1.1 V. (6) Additional power is consumed when the PLL is powered. 8.7 Audio Data Serial Interface Timing Requirements (1) (2) IOVDD = 1.1 V IOVDD = 3.3 V UNIT MIN MAX MIN MAX I2S/LJF/RJF TIMING IN MASTER MODE (See Figure 1) td(WS) ADWS/WCLK delay time 50 15 ns td(DO-WS) ADWS/WCLK to DOUT delay time 50 20 ns td(DO-BCLK) BCLK to DOUT delay time 50 15 ns ts(DI) DIN setup time 10 6 ns th(DI) DIN hold time 10 6 ns tr Rise time 30 10 ns (1) All timing specifications are measured at characterization but not tested at final test. (2) All specifications at 25°C, DVDD = 1.8 V. 10 Submit Documentation Feedback Copyright © 2007–2014, Texas Instruments Incorporated Product Folder Links: TLV320AIC3104 |
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