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TAS5766MRMTR Datasheet(PDF) 10 Page - Texas Instruments |
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TAS5766MRMTR Datasheet(HTML) 10 Page - Texas Instruments |
10 / 84 page TAS5766M, TAS5768M SLAS965C – SEPTEMBER 2013 – REVISED JANUARY 2015 www.ti.com 7.8 Timing Requirements - I 2C Bus Timing MIN MAX UNIT Standard 100 tSCL SCL clock frequency kHz Fast 400 Standard 4.7 tBUF Bus free time between a STOP and START condition µs Fast 1.3 Standard 4.7 tLOW Low period of the SCL clock µs Fast 1.3 Standard 4 tHI High period of th eSCL clock µs Fast 0.6 Standard 4.7 tRS-SU Setup time for (repeated) START condition µs Fast 0.6 tS-HD Standard 4 Hold time for (repeated) START condition µs tRS-HD Fast 0.6 Standard 0.25 tD-SU Data setup time µs Fast 0.1 Standard 0 0.9 tD-HD Data hold time µs Fast 0 0.9 Standard 20+ 0.1CB 1 tSCL-R Rise time of SCL signal µs Fast 20+ 0.1CB 0.3 Standard 20+ 0.1CB 1 Rise time of SCL signal after a repeated START condition and after an tSCL-R1 µs acknowledge bit Fast 20+ 0.1CB 0.3 Standard 20+ 0.1CB 1 tSCL-F Fall time of SCL signal µs Fast 20+ 0.1CB 0.3 Standard 20+ 0.1CB 1 tSDA-R Rise time of SDA signal µs Fast 20+ 0.1CB 0.3 Standard 20+ 0.1CB 1 tSDA-F Fall time of SDA signal µs Fast 20+ 0.1CB 0.3 Standard 4 tP-SU Setup time for STOP condition µs Fast 0.6 CB Capacitive load for SDA and SCL line 400 pF tSP Pulse width of spike suppressed Fast 50 ns Noise margin at high level for each connected device (including VNH 0.2 VDD V hysteresis) Figure 1. Register Access Timing 10 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TAS5766M TAS5768M |
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