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TAS5760MDDCAR Datasheet(PDF) 6 Page - Texas Instruments |
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TAS5760MDDCAR Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 72 page  TAS5760MD SLOS741C – MAY 2013 – REVISED MARCH 2015 www.ti.com 7.4 Thermal Information TAS5760MD THERMAL METRIC(1) UNIT 48 PIN DCA(1) 48 PIN DCA(2) θJA Junction-to-ambient thermal resistance 60.3 30.2 °C/W θJC(top) Junction-to-case (top) thermal resistance 16 14.3 °C/W θJB Junction-to-board thermal resistance 12 12.7 °C/W ψJT Junction-to-top characterization parameter 0.4 0.6 °C/W ψJB Junction-to-board characterization parameter 11.9 12.7 °C/W θJC(bottom) Junction-to-case (bottom) thermal resistance 0.8 0.7 °C/W (1) JEDEC Standard 2 Layer Board (2) JEDEC Standard 4 Layer Board 7.5 Digital I/O Pins over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Input Logic HIGH threshold for DVDD All digital pins except for VIH1 70 %DVDD Referenced Digital Inputs DR_MUTE Input Logic LOW threshold for DVDD All digital pins except for VIL1 30 %DVDD Referenced Digital Inputs DR_MUTE All digital pins except for IIH1 Input Logic HIGH Current Level 15 µA DR_MUTE All digital pins except for IIL1 Input Logic LOW Current Level –15 µA DR_MUTE VOH Output Logic HIGH Voltage Level IOH = 2 mA 90 %DVDD VOL Output Logic LOW Voltage Level IOH = -2 mA 10 %DVDD Input Logic HIGH threshold for DRVDD VIH2 For DR_MUTE Pin 60 %DRVDD Referenced Digital Inputs Input Logic LOW threshold for DRVDD VIL2 For DR_MUTE Pin 40 %DRVDD Referenced Digital Inputs IIH2 Input Logic HIGH Current Level For DR_MUTE Pin 1 µA IIL2 Input Logic LOW Current Level For DR_MUTE Pin –1 µA 7.6 Master Clock over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DMCLK Allowable MCLK Duty Cycle 45% 50% 55% Values include: 128, 192, 256, fMCLK Supported MCLK Frequencies 128 512 fS 384, 512. 7.7 Serial Audio Port over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DSCLK Allowable SCLK Duty Cycle 45% 50% 55% Required LRCK to SCLK Rising Edge 15 ns Required SDIN Hold Time after SCLK tHLD 15 ns Rising Edge Required SDIN Setup Time before SCLK tsu 15 ns Rising Edge Sample rates above 48kHz supported by "double speed fS Supported Input Sample Rates 32 96 kHz mode," which is activated through the I²C control port fSCLK Supported SCLK Frequencies Values include: 32, 48, 64 32 64 fS 6 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TAS5760MD |
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