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TAS5622ADDV Datasheet(PDF) 7 Page - Texas Instruments |
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TAS5622ADDV Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 42 page  TAS5622A www.ti.com SLAS845A – MAY 2012 – REVISED MARCH 2015 6.5 Electrical Characteristics PVDD_X = 32.5 V, GVDD_X = 12 V, VDD = 12 V, TC (Case temperature) = 75°C, fS = 384 kHz, unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION Voltage regulator, only used as a DVDD VDD = 12 V 3.0 3.3 3.6 V reference node Voltage regulator, only used as a AVDD VDD = 12 V 7.8 V reference node Operating, 50% duty cycle 20 IVDD VDD supply current mA Idle, reset mode 20 50% duty cycle 12 IGVDD_X Gate-supply current per full-bridge mA Reset mode 3 50% duty cycle without load 12 IPVDD_X Full-bridge idle current RESET low 1.7 mA VDD and GVDD_X at 0V 0.35 OUTPUT-STAGE MOSFETs Drain-to-source resistance, low side RDS(on), LS 40 m Ω (LS) TJ = 25°C, excludes metallization resistance, GVDD = 12 V Drain-to-source resistance, high side RDS(on), HS 40 m Ω (HS) I/O PROTECTION Vuvp,GVDD 8.5 V Undervoltage protection limit, GVDD_X Vuvp,GVDD, hyst (1) 0.7 V Vuvp,VDD 8.5 V Undervoltage protection limit, VDD Vuvp,VDD, hyst (1) 0.7 V Vuvp,PVDD 8.5 V Undervoltage protection limit, PVDD_X Vuvp,PVDD,hyst (1) 0.7 V OTW(1) Overtemperature warning 115 125 135 °C Temperature drop needed below OTW OTWhyst (1) temperature for OTW to be inactive 25 °C after OTW event. OTE(1) Overtemperature error 145 155 165 °C OTE-OTWdifferential (1) OTE-OTW differential 30 °C A device reset is needed to clear OTEHYST (1) 25 °C FAULT after an OTE event OLPC Overload protection counter fPWM = 384 kHz 2.6 ms Resistor – programmable, nominal peak current in IOC Overcurrent limit protection 15 A 1 Ω load, ROC = 24 kΩ Resistor – programmable, nominal peak current in IOC_LATCHED Overcurrent limit protection, latched 15 A 1 Ω load, ROC = 62 kΩ Time from application of short condition to Hi-Z of IOCT Overcurrent response time 150 ns affected half bridge Internal pulldown resistor at output of Connected when RESET is active to provide IPD 3 mA each half bridge bootstrap charge. Not used in SE mode. STATIC DIGITAL SPECIFICATIONS VIH High level input voltage 1.9 V INPUT_X, M1, M2, M3, RESET VIL Low level input voltage 0.8 V LEAKAGE Input leakage current 100 μA OTW / SHUTDOWN (FAULT) Internal pullup resistance, OTW, CLIP, RINT_PU 20 26 33 k Ω FAULT to DVDD VOH High level output voltage Internal pullup resistor 3 3.3 3.6 V VOL Low level output voltage IO = 4mA 200 500 mV FANOUT Device fanout OTW, FAULT, CLIP No external pullup 30 devices (1) Specified by design. Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: TAS5622A |
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