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AS5047P-ATSM Datasheet(PDF) 9 Page - ams AG |
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AS5047P-ATSM Datasheet(HTML) 9 Page - ams AG |
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9 / 40 page  ams Datasheet Page 9 [v1-00] 2014-Oct-31 Document Feedback AS5047P − Detailed Description The AS5047P is a Hall-effect magnetic sensor using a CMOS lateral technology. The lateral Hall sensors convert the magnetic field component perpendicular to the surface of the chip into a voltage. The signals from the Hall sensors are amplified and filtered by the analog front-end (AFE) before being converted by the analog-to-digital converter (ADC). The output of the ADC is processed by the hardwired CORDIC (coordinate rotating digital computer) block to compute the angle and magnitude of the magnetic vector. The intensity of the magnetic field (magnitude) is used by the automatic gain control (AGC) to adjust the amplification level for compensation of the temperature and magnetic field variations. The internal 14-bit resolution is available by reading a register through the SPI interface. The resolution on the ABI output can be programmed from 4096 to 100 steps per revolution. The Dynamic Angle Error Compensation block corrects the calculated angle for latency using a linear prediction calculation algorithm. At constant rotation speed the latency time is internally compensated by the AS5047P, reducing the dynamic angle error at the SPI, ABI and UVW outputs. The AS5047P allows to switch OFF the UVW output interface to display the absolute angle as PWM-encoded signal on the pin W. At higher speeds, the interpolator fills in missing ABI pulses and generates the UVW signals with no loss of resolution. The non-volatile settings in the AS5047P can be programmed through the SPI interface without any dedicated programmer. The AS5047P is built for high speed application up to 28krpm. Power Management The AS5047P can be either powered from a 5.0V supply using the on-chip low-dropout regulator or from a 3.3V voltage supply. The LDO regulator is not intended to power any other loads, and it needs a 1 μF capacitor to ground located close to the chip for decoupling as shown in Figure 10. In 3.3V operation, VDD and VREG must be tied together. Detailed Description |
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