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54AC273L Datasheet(PDF) 1 Page - National Semiconductor (TI) |
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54AC273L Datasheet(HTML) 1 Page - National Semiconductor (TI) |
1 / 8 page 54AC273 Octal D Flip-Flop General Description The ’273 has eight edge-triggered D-type flip-flops with indi- vidual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) input load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D in- put, one setup time before the LOW-to-HIGH clock transi- tion, is transferred to the corresponding flip-flop’s Q output. All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. The de- vice is useful for applications where the true output only is re- quired and the Clock and Master Reset are common to all storage elements. Features n Ideal buffer for microprocessor or memory n Eight edge-triggered D flip-flops n Buffered common clock n Buffered, asynchronous master reset n See ’377 for clock enable version n See ’373 for transparent latch version n See ’374 for TRI-STATE® version n Outputs source/sink 24 mA n ’ACT has TTL-compatible inputs n Standard Military Drawing (SMD) — ’AC273: 5962-87756 Logic Symbols Pin Names Description D 0–D7 Data Inputs MR Master Reset CP Clock Pulse Input Q 0–Q7 Data Outputs TRI-STATE® is a registered trademark of National Semiconductor Corporation. FACT™ is a trademark of National Semiconductor Corporation. DS100288-1 IEEE/IEC DS100288-2 July 1998 © 1998 National Semiconductor Corporation DS100288 www.national.com 1 PrintDate=1998/07/27 PrintTime=08:02:05 44014 ds100288 Rev. No. 1 cmserv Proof 1 |
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