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CY7C130/CY7C131
CY7C140/CY7C141
8
Note:
23. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state
Switching Waveforms (continued)
Write Cycle No. 2 (R/W Three-States Data I/Os - Either Port)
tAW
tWC
tSCE
tSA
tPWE
tHD
tSD
tHZWE
Either Port
tHA
HIGH IMPEDANCE
ADDRESS MATCH
tPS
Busy Timing Diagram No. 1 (CE Arbitration)
CEL Valid First:
tBLC
tBHC
ADDRESS MATCH
tPS
tBLC
tBHC
CER Valid First:
DATA VALID
tLZWE
C130-11
C130-12
C130-13
ADDRESS
CE
R/W
DATAOUT
DATAIN
ADDRESSL,R
BUSYR
CEL
CER
BUSYL
CER
CEL
ADDRESSL,R
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