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CY7C130/CY7C131
CY7C140/CY7C141
7
Notes:
21. Address valid prior to or coincident with CE transition LOW.
22. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or tHZWE + tSD to allow the data I/O pins to enter high impedance and for data
to be placed on the bus for the required tSD.
Switching Waveforms (continued)
tACE
tLZOE
tDOE
tHZOE
tHZCE
DATA VALID
DATA OUT
CE
OE
tLZCE
tPU
ICC
ISB
tPD
Read Cycle No. 2
tBHA
tBDD
VALID
tDDD
tWDD
ADDRESS MATCH
ADDRESS MATCH
R/WR
ADDRESSR
DINR
ADDRESSL
BUSYL
DOUTL
Read Cycle No.3
Write Cycle No.1 (OE Three-States Data I/Os - Either Port)
tAW
tWC
DATA VALID
HIGH IMPEDANCE
tSCE
tSA
tPWE
tHD
tSD
tHA
CE
R/W
ADDRESS
tHZOE
OE
DOUT
DATAIN
Either Port CE/OE Access
Either Port
C130-8
C130-9
C130-10
tPS
tBLA
Read with BUSY, Master: CY7C130 and CY7C131
tRC
tPWE
VALID
tHD
[19, 21]
[20]
[15, 22]