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X4003M8I Datasheet(PDF) 8 Page - Intersil Corporation |
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X4003M8I Datasheet(HTML) 8 Page - Intersil Corporation |
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8 / 16 page  8 FN8113.2 June 30, 2008 Serial Start Condition All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. See Figure 7. Serial Stop Condition All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the device into the Standby power mode after a read sequence. A stop condition can only be issued after the transmitting device has released the bus. See Figure 7. Serial Acknowledge Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. Refer to Figure 8. The device will respond with an acknowledge after recognition of a start condition and the correct contents of the slave address byte. Acknowledge bits are also provided by the X4003/4005 after correct reception of the control register address byte, after receiving the byte written to the control register and after the second slave address in a read question (see Figures 9 and 10). Serial Write Operations Slave Address Byte Following a start condition, the master must output a slave address byte. This byte consists of several parts: • a device type identifier that is always ‘1011’. • two bits of ‘0’. • one bit of the slave command byte is a R/W bit. The R/W bit of the slave address byte defines the operation to be SCL SDA START STOP FIGURE 7. VALID START AND STOP CONDITIONS DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER 8 1 9 START ACKNOWLEDGE SCL FROM MASTER FIGURE 8. ACKNOWLEDGE RESPONSE FROM RECEIVER 0 SLAVE ADDRESS BYTE ADDRESS DATA A C K A C K A C K SDA BUS SIGNALS FROM THE SLAVE SIGNALS FROM THE MASTER 1 0 0 1 1 0 11 1 1 1 1 1 1 1 FIGURE 9. WRITE CONTROL REGISTER SEQUENCE X4003, X4005 |
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