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71256L25YGI8 Datasheet(PDF) 8 Page - Integrated Device Technology |
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71256L25YGI8 Datasheet(HTML) 8 Page - Integrated Device Technology |
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8 / 10 page  8 IDT71256S/L CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,4,6) NOTES: 1. A write occurs during the overlap of a LOW CS and a LOW WE. 2. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle. 3. During this period, I/O pins are in the output state so that the input signals must not be applied. 4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 5. Transition is measured ±200mV from steady state. 6. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ +tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse width can be as short as the specified tWP. For a CS controlled write cycle, OE may be LOW with no degradation to tCW. Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,2,4) CS 2946 drw 10 tAW tWR tDW DATAIN ADDRESS t WC WE t WP tDH DATAOUT tWZ t t AS (5) (3) OE (3) (6) OW tOHZ (5) t WR CS 2946 drw 11 tAW tDW DATAIN ADDRESS tWC WE tCW tDH2 AS t t (6) |
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