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TCC-202A-RT Datasheet(PDF) 7 Page - ON Semiconductor |
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TCC-202A-RT Datasheet(HTML) 7 Page - ON Semiconductor |
7 / 23 page TCC−202 www.onsemi.com 7 AVDD Power−On Reset (POR) Upon application of AVDD the TCC−202 will be in shutdown mode. All circuit blocks are off and the chip draws only minimal leakage current. VIO Power−On Reset and Startup Conditions A high level on VIO places the chip in startup mode which provides a POR to the TCC−202. POR resets all registers to their default settings as described in Table 8. VIO POR also resets the serial interface circuitry. POR is not a brown−out detector and VIO needs to be brought back to a low level to enable the POR to trigger again. Table 7. VIO POWER−ON RESET AND STARTUP Register Default State for VIO POR Comment DAC Boost [1011] VHV = 24 V Power Mode [01]>[00] Transitions from shutdown to startup and then automatically to active mode DAC Enable [000000] VOUT A, B Disabled DAC A Output in High−Z Mode DAC B Output in High−Z Mode VIO Shutdown A low level at any time on VIO places the chip in shutdown mode in which all circuit blocks are off. The contents of the registers are not maintained in shutdown mode. Table 8. VIO THRESHOLDS (AVDD from 2.3 V to 5.5 V; TA = –30 to +85°C unless otherwise specified) Parameter Description Min Typ Max Unit Comments VIORST VIO Low Threshold − − 0.2 V When VIO is lowered below this threshold level the chip is reset and placed into the shutdown state Power Supply Sequencing The AVDD input is typically directly supplied from the battery and thus is the first on. After AVDD is applied and before VIO is applied to the chip, all circuits are in the shutdown state and draw minimum leakage currents. Upon application of VIO, the chip automatically starts up using default settings and is placed in the active state waiting for a command via the serial interface. Table 9. TIMING (AVDD from 2.3 V to 5.5 V; VIO from 1.62 V to 1.98 V; TA = –30 to +85°C; OUT A and OUT B; CHV = 47 nF; LBOOST = 15 mH; VHV = 24 V; Turbo−Charge mode off unless otherwise specified; VDDA = 1.7 V) Parameter Description Min Typ Max Unit Comments TPOR_VREG Internal bias settling time from shutdown to active mode − 50 120 ms For info only TBOOST_START Time to charge CHV @ 80% of set VHV (set to 24 V, VDDA = 2.7 V) − 130 − ms For info only TSD_TO_ACT Startup time from shutdown to active mode − 180 300 ms TSET+ Output A, B positive settling time to within 5% of the delta voltage, equivalent series load of 5.6 k W and 2.7 nF, VOUT from 2 V to 20 V; 0Bh (11d) to 55h (85d) − 50 60 ms Voltage settling time connected on VOUT A, B TSET− Output A, B negative settling time to within 5% of the delta voltage, equivalent series load of 5.6 k W and 2.7 nF, VOUT from 20 V to 2 V; 55h (85d) to 0Bh (11d) − 50 60 ms Voltage settling time connected on VOUT A, B TSET+ Output A, B positive settling time with Turbo − 35 − ms Voltage settling time connected on VOUT A, B TSET− Output A, B negative settling time with Turbo − 35 − ms Voltage settling time connected on VOUT A, B |
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