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961102-6404-AR Datasheet(PDF) 4 Page - Integrated Device Technology |
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961102-6404-AR Datasheet(HTML) 4 Page - Integrated Device Technology |
4 / 27 page Matched Broadband RF VGA 400MHz to 2700MHz Glitch-Free TM, Zero-DistortionTM, RF VGA 4 Rev 3, April 2015 IDTF0480NBGI Datasheet IDTF0480 SPECIFICATION See F0480 Typical Application Circuit. Specifications apply when operated as an RF DVGA, VCC = +5.00 V, TC = +25 °C, Max gain setting, output power = 0 dBm, ZRFI = ZRFO = 50 Ω, unless otherwise noted. Parameter Symbol Conditions Min Typ Max Units Logic Input High VIH JEDEC 3.3V logic 2.0 1 V Logic Input Low VIL JEDEC 3.3V logic 0.8 V Logic Input High VIH JEDEC 1.8V logic 1.1 V Logic Input Low VIL JEDEC 1.8V logic 0.63 V Logic Current IIH, IIL STBY, Band_Select -10 +10 µA SPI_ -4 +4 Logic CTL -35 +35 Supply Current 3 ICC_LB Low Band Configuration 100 mA ICC_MB Mid Band Configuration 117 128 ICC_HB High Band Configuration 109 ICC_STBY Standby Mode 1.3 1.7 Startup time 50% of STBY going low to Gain within ± 1 dB with no attenuation. 250 ns Gain adjustment range GADJ 23 dB Gain step GSTEP 1 dB Max Attenuator Glitch ATTNG Step from 15 to 16 dB or 16 to 15 dB 0.5 dB Gain Settling Time GST 50% of CSb to ± 0.1 dB of settled gain 500 ns Serial Clock Speed 10 MHz CSb to first serial clock rising edge A SPI 3 wire Bus. 50% of CSb falling edge to 50% of CLK rising edge. 10 ns Serial Data Hold Time B SPI 3 wire Bus. 50% of CLK rising edge to 50% of Data falling edge. 10 ns Final serial clock rising edge to CSb C SPI 3 wire Bus. 50% of CLK rising edge to 50% of CSB rising edge. 10 ns Note 1: Items in min/max columns in bold italics are Guaranteed by Test. Note 2: Items in min/max columns that are not bold/italics are Guaranteed by Design Characterization. Note 3: During standby mode, SPI is to be left ON and previous state shall be maintained when device is powered up. |
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