Matched Broadband RF VGA

400MHz to 2700MHz

Glitch-Free

4

Rev 3, April 2015

IDTF0480NBGI

Datasheet

Parameter

Symbol

Conditions

Min

Typ

Max

Units

Logic Input High

JEDEC 3.3V logic

2.0

1

V

Logic Input Low

JEDEC 3.3V logic

0.8

V

Logic Input High

JEDEC 1.8V logic

1.1

V

Logic Input Low

JEDEC 1.8V logic

0.63

V

Logic Current

STBY, Band_Select

-10

+10

µA

SPI_

-4

+4

Logic CTL

-35

+35

Supply Current

3

Low Band Configuration

100

mA

Mid Band Configuration

117

128

High Band Configuration

109

Standby Mode

1.3

1.7

Startup time

50% of STBY going low to

Gain within ± 1 dB with no

attenuation.

250

ns

Gain adjustment range

23

dB

Gain step

1

dB

Max Attenuator Glitch

Step from 15 to 16 dB or 16 to

15 dB

0.5

dB

Gain Settling Time

50% of CSb to ± 0.1 dB of

settled gain

500

ns

Serial Clock Speed

10

MHz

CSb to first serial clock

rising edge

A

SPI 3 wire Bus. 50% of CSb

falling edge to 50% of CLK

rising edge.

10

ns

Serial Data Hold Time

B

SPI 3 wire Bus. 50% of CLK

rising edge to 50% of Data

falling edge.

10

ns

Final serial clock rising

edge to CSb

C

SPI 3 wire Bus. 50% of CLK

rising edge to 50% of CSB

rising edge.

10

ns

Note 1: Items in min/max columns in

Note 2: Items in min/max columns that are not bold/italics are Guaranteed by Design Characterization.

Note 3: During standby mode, SPI is to be left ON and previous state shall be maintained when device is powered up.