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NLAS54404 Datasheet(PDF) 10 Page - ON Semiconductor

Part # NLAS54404
Description  Ultra-Low THD Stereo SPDT Switch
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

NLAS54404 Datasheet(HTML) 10 Page - ON Semiconductor

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NLAS54404
www.onsemi.com
10
Detailed Description
The NLAS54404 is a single supply, bidirectional, dual
single pole/double throw (SPDT) ultra−low distortion, high
OFF−Isolation analog switch. It was designed to operate
from a 3.3 V single supply. The switches can accommodate
±2.828 VPEAK (2 VRMS) ground−referenced analog signals.
The switch rON flatness across this range is extremely small
resulting in excellent THD+N performance (0.00013% with
20 k
W load and 0.00039% with 32 W load at 707 mVRMS).
The NLAS54404 was designed primarily for consumer
and professional audio switching applications such as
computer sound cards and home theater products. The
“Sound Card Application Block Diagrams” show two
typical sound card applications. In the upper block diagram,
the NLAS54404 is being used to route a single stereo source
to either the front or back panel line outs of the computer
sound card. In the lower block diagram, the NLAS54404 is
being used to multiplex two stereo sources to a single line out
of the computer sound card.
SPDT Switch Cell Architecture and Performance
Characteristics
The normally open (L2, R2) and normally closed (L1, R1)
of the SPDT switches have a typical rON of 2.1
W and an
OFF−isolation of > 113 dB. The low on−resistance (2.1
W
and rON flatness (0.021
W) provide very low insertion loss
and minimal distortion to applications that require
hi−fidelity signal reproduction.
The SPDT switch cells have internal charge pumps that
allow for signals to swing below ground. They were
specifically designed to pass audio signals that are ground
referenced and have a swing of
±2.828 VPEAK while driving
either 10 k / 20 k
W (receiver) or 32 W (headphone) loads.
Each switch cell incorporates special circuitry to delay the
switch transition from the OFF−state (high impedance) to
the ON−state (2.1
W). This turn−on delay may help reduce
clicks and pops in the speaker by matching turn−on time to
transient switching events. The turn−on delay time is
determined by the capacitor value of the delayed turn−on
capacitor connected at the CAP_SS pin, the speaker load and
the DC level of the audio signal. With a 0.1
mF ceramic chip
capacitor, a 32
W load and 1.5 V DC level, the turn−on delay
is approximately 1810
ms. The turn−on delay may be
disabled by floating the CAP_SS pin.
Supply Voltage, Signal Amplitude, and Grounding
The power supply connected at VDD pin provides power
to the NLAS54404 part. The NLAS54404 is a single supply
device that was designed to be operated with a 3.0 V to 3.6 V
DC supply connected at the VDD pin. It was specifically
designed
to
accept
ground
referenced
2 VRMS
(
±2.828 VPEAK) audio signals at its signal pins while
driving either 10 k / 20 k
W receiver loads or 32 W headphone
loads.
When using the part in an application, a 0.1
mF decoupling
capacitor should be connected from the VDD pin to ground
to minimize power supply noise and transients. This
capacitor should be located as close to the pin as possible.
Mute Operation
When the MUTE logic pin is driven HIGH, the part will
go into the mute state. In the mute state, all switches of the
SPDTs are open. See “Logic Control” below for more
details.
Mute to On
When the MUTE pin is driven LOW, the resistance of the
switches selected by the SEL_x pin will go from high OFF
resistance to their ON resistance of 2.1
W after a certain time
delay.
The turn−on delay time is determined by the capacitor
value of the delayed turn−on capacitor connected at the
CAP_SS pin, the speaker load and the DC level of the audio
signal. See Figures 26 and 27.
Table 3 indicates how mute to ON delay is affected by the
CAP_SS capacitor value and the switch input DC voltage
level.
Table 3. SIGNAL TURN−ON DELAY FOR A 32
W LOAD
Capacitor Value
VIS DC Level
Turn−On Delay
No Capacitor
1.5 V
30.2
ms
0.05
mF
1.5 V
564
ms
0.1
mF
1.5 V
1810
ms
No Capacitor
60 mV
27.6
ms
0.05
mF
60 mV
40
ms
0.1
mF
60 mV
56.4
ms
On to Mute
When the MUTE pin is driven HIGH, the switches will
turn off quickly (245 ns).
Logic Control
The NLAS54404 has three logic control pins; MUTE,
SEL_L and SEL_R. The MUTE, SEL_L and SEL_R control
pins determine the state of the switches.
The NLAS54404 logic is 1.8 V CMOS compatible (Low
≤ 0.5 V and High ≥ 1.4 V) over a supply range of 3.0 V to
3.6 V at the VDD pin. This allows control via 1.8 V or 3 V
m−controller.
SEL_L, SEL_R, Mute Control Pins
The state of the SPDT switches of the NLAS54404 device
is determined by the voltage at the MUTE, SEL_L SEL_R
pins. The SEL_L and SEL_R control pins are only active
when MUTE is logic “0”. The MUTE has an internal
pull−up resistor to the internal 3.3 V supply rail and can be
driven HIGH or tri−stated (floated) by the
m−processor.
These pins are 1.8 V logic compatible. When powering
the part by the VDD pin, the logic voltage can be as high as
the VDD voltage which is typically 3.3 V.


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