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TM1IO Datasheet(PDF) 11 Page - Panasonic Semiconductor |
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TM1IO Datasheet(HTML) 11 Page - Panasonic Semiconductor |
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11 / 25 page  MN103SFM9K 32-bit Single-chip Microcontroller Publication date: August 2014 11 PubNo. 232M9-010E 1.3.3 Pin Functions Table:1.3.2 Pin Functions Name TQFP 48 Pin No. I/O Other Function Function Description VDD VDD VDD VDD VDD 17 40 41 65 94 - Power supply pin Power pin for 5 V, digital IO. Apply 5 V to all of pins and connect capacitor of over 10 μF between all of the VDD and VSS pins. (allocate near the pins) It is recommended that total capacitance between all of the VDD and VSS is more than 10-times capacitance between all of the VDD2 and VSS. VDD2 VDD2 42 98 - Power supply pin Power pin for 1.8 V, digital IO Connect capacitor of over 1 μF between all of the VDD2 and VSS pins. (allocate near the pins) VSS VSS VSS VSS 15 38 67 96 - Power supply pin GND for digital VPPEX 39 - Power supply pin Power for flash EEPROM Connect with VDD. OSC1 OSC0 37 36 input output - Clock input pin Clock output pin Extend ceramic or crystal oscillators or input a clock to OSC1. NRST 48 input - Reset pins (negative logic) This pin resets the chip when power is turned on and contains an internal pull-up resistor. Setting this pin “L” level initialize the internal state of the device. Thereafter, setting the input to “H” level releases the reset. The hardware waits for the system clock to stabilize, then processes the reset interrupt. Connect capacitor of over 0.1 μF between NRST and VSS pins. P10 P11 P12 P13 P14 P15 P16 P17 43 44 45 46 47 49 50 51 I/O IRQ04/ EXTRG0 IRQ05/ EXTRG1 IRQ06 IRQ07 IRQ08 TM6IO TM7IO SBO2 I/O port 1 8-bit CMOS I/O port. Each bit can be set individually as either an input or output by the P1DIR register. A pull-up resistor for each bit can be selected individually by the P1PLU register. At reset, the input mode (P10 to P17) is selected, and pull-up resistor is disable. P20 P21 P22 P23 P24 P25 P26 P27 52 53 54 55 56 57 58 59 I/O SBT2 SBI2 SBO1 SBT1 SBI1 SBO0 SBT0 SBI0 I/O port 2 8-bit CMOS I/O port. Each bit can be set individually as either an input or output by the P2DIR register. A pull-up resistor for each bit can be selected individually by the P2PLU register. At reset, the input mode (P20 to P27) is selected, and pull-up resistor is disable. P30 P31 P32 P33 P34 P35 P36 P37 60 61 62 63 64 66 68 69 I/O TM0IO TM1IO TM2IO TM3IO TM4IO TM5IO TM8AIO TM8BIO I/O port 3 8-bit CMOS I/O port. Each bit can be set individually as either an input or output by the P3DIR register. A pull-up resistor for ech bit can be selected individually by the P3PLU register. At reset, the input mode (P30 to P37) is selected, pull-up resistor is disable. |
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