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MN103LF66 Datasheet(PDF) 5 Page - Panasonic Semiconductor |
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MN103LF66 Datasheet(HTML) 5 Page - Panasonic Semiconductor |
5 / 102 page MN103LF66/67/68/69/70/71/72/73/74/75/76/77/78/79 Series 32-bit Single-chip Microcontroller Publication date: November 2015 5 PubNo. 2347901-012E Internal operation clock: 6 types CPU clock (clkcpu) Frequency : 48 MHz (Max) Clock source : clkplldiv, clkosc, clkrc, clkx Clock dividing : 1, 2, 4, 8, 16, 32, 64 divided of clock source Peripheral bus clock (clkbus) Frequency : 24 MHz (Max) Clock source : clkplldiv, clkosc, clkrc, clkx Clock dividing : 2, 4, 8, 16, 32, 64, 128 divided of clock source (This setting is independent from the dividing clock setting of clkcpu. Set the frequency of clkbus to less than clkcpu.) Peripheral high-speed clock (clksp) Frequency : 24 MHz (Max) Clock source : clkrc, clkosc, clkplldiv Clock dividing : 1, 2, 4, 8, 16 divided of clock source High-speed oscillation clock (clkoscsel) Frequency : 22 MHz (Max) Clock source : clkrc, clkosc Internal low-speed oscillation clock (clkrcx) Frequency : 33 kHz (Max) Low-speed oscillation clock (clksx) Frequency : 39.0625 kHz (Max) Clock source : clkrcx, clkxsel External bus interface Bus area : 2 MB 2 banks Data bus : 8/ 16 bits |
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