Ver. AEM

MN101E50 Series

5



Features (continued)

<Timer 7> (General-purpose 16-bit timer)

Clock source:

fpll-div, fs, external clock, Timer A output, Serial Interface 0 transfer clock output,

Timer 6 compare match cycle divided by 1, 2, 4, 16

Hardware configuration:

Double-buffered compare register (×2)

Double-buffered input capture register (×2)

Timer interrupt (×2 vector)

Timer function

Square wave output (Timer pulse output), high-precision PWM output (cycle/duty continuous changeable),

large current selectable, timer synchronous output, event count, input capture function (both edges operable)

Real-time control

Timer (PWM) output is controlled among the three values: "Fixed to High", "Fixed to Low" or "Hi-Z" at falling edge of

External Interrupt 0 (IRQ0)

<Timer 8> (General-purpose 16-bit timer)

Clock source:

fpll-div, fs, external clock, Timer A output, Timer 6 compare match cycle divided by 1, 2, 4, 16

Hardware configuration

Double-buffered compare register (×2)

Input capture register (×1)

Timer interrupt (×2 vector)

Timer function

Square wave output (Timer pulse output), high-precision PWM output (cycle/duty continuous changeable),

large current selectable, event count, pulse width measurement, input capture function (both edges operable)

32-bit cascade connection (connected with Timer 7), 32-bit PWM output, input capture is available in 32-bit cascade

<Timer A> (baud rate timer)

Clock output for peripheral functions

Clock source:

fpll-div divided by 1, 2, 4, 8, 16, 32, fs divided by 2, 4

<24H timer>

Clock source (Usable frequency):

fpll (4 MHz, 4.19 MHz, 5 MHz, 8 MHz, 8.38 MHz, 10 MHz, 16 MHz, 16.77 MHz, 20 MHz), fx (32.768 kHz),

frc (20 MHz, 16 MHz)

Hardware configuration

0.5 second counter, minute counter, hour counter

Alarm compare register (in 0.5 second, in minutes, in hours) (×1)

Timer interrupt (×2 vector)

Timer Function

Interval function (interrupts every 0.5 second, 1 second, 1 minute, 1 hour, 24 hours)

Alarm function

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Watchdog timer

System reset is generated by the hardware when software processing error is detected twice.

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Synchronous output function (Timer synchronous output, interrupt synchronous output)

Latch data is output from Port 8 at the event timing of synchronous output signal of Timer 1, Timer 2, Timer 7,

or external interrupt 2 (IRQ2)