NCP308, NCV308

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2

VDD

SENSE

−

Vref

+

Control Logic

and Timer

CT

90k

VDD

Adjustable Versions

NCP308SNADJ/NCP308MTADJ

SENSE

VDD

−

Vref

+

CT

Control Logic

and Timer

90k

VDD

NCP308SNXXX/NCP308MTXXX

Fixed Versions

R1

R2

Figure 3. Functional Block Diagrams of Adjustable and Fixed Versions

MR

RESET

MR

RESET

Figure 4. Pin Connections Diagram (Top View)

1

2

3

6

5

4

GND

VDD

SENSE

CT

RESET

MR

1

2

3

6

5

4

VDD

SENSE

CT

RESET

MR

GND

Table 1. PIN OUT DESCRIPTION

Name

Pin Number

Description

TSOP−6

WDFN6

VDD

6

1

Supply Voltage. A 0.1uF ceramic capacitor placed close to this pin is helpful for transient and

parasitic.

SENSE

5

2

Sense Input, this is the voltage to be monitored. If the voltage at this terminal drops below the

monitor any voltage lower than VDD.

CT

4

3

Reset Delay Time Setting Pin. Connecting this pin to VDD through a 40 k

W to 200 kW resistor or

leaving it open results in fixed reset delay times. Connecting this pin to a ground referenced

capacitor (

≥ 100 pF) gives a user−programmable reset delay time. See the Setting Reset Delay

Time section for more information.

MR

3

4

Manual Reset input, MR low asserts RESET. MR is internally tied to VDD by a 90 k

W pull−up

Resistor.

RESET

1

6

RESET Output, is an Active low open drain N−Channel MOSFET output, it is driven to a low

impedance state when RESET is asserted (either the SENSE input is lower than the threshold

10k

W to 1MW should be used on this pin. See Figure 5 for behavior of RESET depends on VDD,

SENSE and MR conditions.

GND

2

5

Ground terminal. Should be connected to PCB ground reference

EXP

PAD

−

Exposed

Pad

Exposed pad, under WDFN6 package, connect it to ground plane for better thermal dissipation.