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NB3N2302 Datasheet(PDF) 4 Page - ON Semiconductor

Part # NB3N2302
Description  Frequency Multiplier
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

NB3N2302 Datasheet(HTML) 4 Page - ON Semiconductor

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NB3N2302
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4
Table 5. DC CHARACTERISTICS VDD = 3.3 V ± 5% or 5 V ± 10%, GND = 0 V, TA = −40°C to +85°C
Symbol
Characteristic
Min
Typ
Max
Unit
IDD
Power Supply Current, 100 MHz, Unloaded Outputs VDD = 3.3 V $ 5%
VDD = 5 V $ 10%
20
25
35
50
mA
VOH
Output HIGH Voltage IOH = −12 mA
2.4
V
VOL
Output LOW Voltage IOL = 12 mA
0.4
V
VIH
Input HIGH Voltage
2.0
V
VIL
Input LOW Voltage
0.8
V
IIH
Input HIGH Current, VIN = VDD
5
mA
IIL
Input LOW Current, VIN = 0 V
VDD = 3.3 V $ 5%
VDD = 5 V $ 10%
−40
−80
5
5
mA
Table 6. AC CHARACTERISTICS VDD = 3.3 V ± 5% or 5 V ± 10%, GND = 0 V, TA = −40°C to +85°C (Note 5)
Symbol
Characteristic
Min
Typ
Max
Unit
fIN
Input Frequency (Note 3)
5
133
MHz
fOUT
Output Frequency, OUT1 15 pF load
10
133
MHz
tD
Output Duty Cycle @ 1.4 V, 120 MHz, 50% duty cycle in, 15 pF load
40
50
60
%
tr/tf
Output rise and fall times; 0.8 V to 2.0V, 15 pF load VDD = 3.3 V $ 5%
VDD = 5 V $ 10%
3.5 / 2.5
2.5 / 1.5
ns
tINCLK
tr/tf
Input Clock rise and fall time (Note 4)
10
ns
tLOCK
PLL Lock Time, power supply stable
1.0
ms
tJC
Cycle−to−cycle Jitter
OUT1, fOUT > 30 MHz
OUT2, fOUT > 30 MHz
115
65
300
300
ps
tDC
Die “Fave Away” Out Time. 33 MHz reference input suddenly stopped
(0 MHz). Number of cycles provided prior to output falling to < 16 MHz.
100
Clock
Cycles
tpd
Propagation Delay, (Note 10)
−350
350
ps
tskew
Output−to−output skew; (Note 6)
25
250
ps
3. Input frequency is limited by output frequency range and input to output frequency multiplication factor (which is determined by circuit
configuration). See Table 1.
4. Longer input rise and fall time degrades skew and jitter performance.
5. All AC specifications are measured with a 50 W transmission line, load terminated with 50 W to 1.4 V.
6. Skew is measured at 1.4 V on rising edges, all outputs with equal loading.
7. Duty cycle is measured at 1.4 V.
8. 33 MHz reference input suddenly stopped (0 MHz). Number of cycles provided prior to output falling to < 16 MHz.
9. Duty Cycle measured at 120 MHz. For 133 MHz, degrades to 35/65 worst case.
10.While in lock, propagation delay is measured from REF_IN to OUT1 using < 1 in feedback trace, (See Figure 1).


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