LV8121V

No.A2135-10/14

Description of LV8121V

1. Motor Drive Output Circuit

The LV8121V provides a charge pump circuit and implements both upper side and lower side N-channel power FET

drive circuit. This IC employs the direct PWM drive technique. The motor speed is controlled by changing the output

duty according to an analog voltage input (CTL). The upper side N-channel power FET is switched so that the output

duty tracks the CTL voltage.

The PWM frequency is determined by the capacitor connected between the PWM pin and GND1.

When the PWM switching of the upper side N-channel power FET is off, the lower side N-channel power FET is

turned on (synchronous rectification). Therefore, it is possible to reduce the temperature increase of the lower side

N-channel power FET.

2. PWM Oscillator

The PWM frequency is set by the oscillation frequency of the PWM pin. When a capacitor C [F] is connected between

the PWM pin and GND1, the PWM frequency (fPWM) is calculated as follows.

fPWM = 1/(28900

× C)

When a 1800pF capacitor is connected, this frequency becomes about 19kHz.

By the variance of the IC, “28900” of the above formula has varied from 22400 to 36800.

If the PWM frequency is too high, since the switching power loss will be large, the IC temperature increase will be

excessive. The PWM frequency therefore should be normally kept below 50kHz, which is achieved with a capacitor C

of 1000pF or higher. The GND lead of the connected capacitor to the PWM pin should be connected as close as

possible to the GND1 pin.

3. Output Duty

The CTL voltage and the PWM oscillation waveform are compared to determine the output duty of the upper side

N-channel power FET.

If the LIM pin is not used (LIM=GND), the output duty becomes 0% when the CTL voltage is lower than about 1.3V

and 100% when it exceeds about 3.1V.

For the application that inputs a fixed voltage to the LIM pin, the LIM voltage and the PWM oscillation waveform are

compared to determine the minimum output duty. Accordingly, even if the CTL voltage is lower than the LIM voltage,

the output duty does not decrease below the minimum output duty.

If a minus voltage is applied to the CTL pin, this pin current must be limited within 2mA by inserting the resistor of

about 200

Ω.

When the CTL pin is open, the output duty becomes 100%. Therefore, connect a pull-down resistor to prevent open.

If the output duty is fast reduced by dropping the CTL voltage quickly when the motor speed is changed from high to

low, since this IC employs the synchronous rectification, the lower side N-channel power FET can be the short brake

condition that turns on two phases. If the lower side N-channel power FET (synchronous rectification) is switched

from on to off while this condition, the motor current may flow on the power supply side, and the power supply

voltage may bounce. The bounce of the power supply voltage is different on the motor speed, the varied range of the

CTL voltage and the capacitance of the power supply line. Therefore, check sufficiently that the bounce of the power

supply voltage does not exceed the maximum rating when the CTL voltage is changed.

Continued on next page.

CTL voltage

LIM voltage

PWM oscillation waveform

OFF

ON

compared result

OFF

ON

Upper side FET

(PWM)

Lower side FET

(synchronous rectification)