TCC−106

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7

AVDD Power−On Reset (POR)

Upon application of AVDD the TCC−106 will be in

shutdown mode. All circuit blocks are off and the chip draws

only minimal leakage current.

VIO Power−On Reset and Startup Conditions

A high level on VIO places the chip in startup mode which

provides a POR to the TCC−106. POR resets all registers to

their default settings as described in Table 8. VIO POR also

resets the serial interface circuitry. POR is not a brown−out

detector and VIO needs to be brought back to a low level to

enable the POR to trigger again.

Table 7. VIO POWER−ON RESET AND STARTUP

Register

Default State for

VIO POR

Comment

DAC Boost

[1111]

VHV = 24 V

Power Mode

[01]>[00]

Transitions from shutdown to startup and then automatically to active mode

DAC Enable

[000000]

DAC A

Output in High−Z Mode

DAC B

Output in High−Z Mode

DAC C

Output in High−Z Mode

DAC D

Output in High−Z Mode

DAC E

Output in High−Z Mode

DAC F

Output in High−Z Mode

VIO Shutdown

A low level at any time on VIO places the chip in shutdown mode in which all circuit blocks are off. The contents of the

registers are not maintained in shutdown mode.

Parameter

Description

Min

Typ

Max

Unit

Comments

VIORST

VIO Low Threshold

−

−

0.2

V

When VIO is lowered below this threshold level the

chip is reset and placed into the shutdown state

Power Supply Sequencing

The AVDD input is typically directly supplied from the battery and thus is the first on. After AVDD is applied and before VIO

is applied to the chip, all circuits are in the shutdown state and draw minimum leakage currents. Upon application of VIO, the

chip automatically starts up using default settings and is placed in the active state waiting for a command via the serial interface.

Parameter

Description

Min

Typ

Max

Unit

Comments

Internal bias settling time from shutdown to active mode

−

50

120

ms

For info only

Time to charge CHV @ 95% of set VHV

−

130

−

ms

For info only

Startup time from shutdown to active mode

−

180

300

ms

Output A, B, C, D, E, F positive settling time to within

5% of the delta voltage, equivalent series load of

(11d) to 55h (85d)

−

50

60

ms

Voltage settling time

A, B, C, D, E, F

Output A, B, C, D, E, F negative settling time to within

5% of the delta voltage, equivalent series load of

(85d) to 0Bh (11d)

−

50

60

ms

Voltage settling time

A, B, C, D, E, F

Output A, B, C, D, E, F positive settling time with Turbo

−

35

−

ms

Voltage settling time

A, B, C, D, E, F

Output A, B, C, D, E, F negative settling time with Turbo

−

35

−

ms

Voltage settling time

A, B, C, D, E, F