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LE25S40QE-AH Datasheet(PDF) 7 Page - ON Semiconductor |
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LE25S40QE-AH Datasheet(HTML) 7 Page - ON Semiconductor |
7 / 22 page LE25S40QE www.onsemi.com 7 2. Status Registers The status registers hold the operating and setting statuses inside the device, and this information can be read (status register read) and the protect information can be rewritten (status register write). There are 8 bits in total, and "Table 4 Status registers" gives the significance of each bit. Table 4 Status Registers Bit Name Logic Function Power-on Time Information Bit0 RDY 0 Ready 0 1 Erase/Program Bit1 WEN 0 Write disabled 0 1 Write enabled Bit2 BP0 0 Block protect information Protecting area switch Nonvolatile information 1 Bit3 BP1 0 Nonvolatile information 1 Bit4 BP2 0 Nonvolatile information 1 Bit5 TB 0 Block protect Upper side/Lower side switch Nonvolatile information 1 Bit6 Reserved bits 0 Bit7 SRWP 0 Status register write enabled Nonvolatile information 1 Status register write disabled 2-1. Status register read The contents of the status registers can be read using the status register read command. This command can be executed even during the following operations. Small sector erase, sector erase, chip erase Page program Status register write "Figure 5 Status Register Read" shows the timing waveforms of status register read. Consisting only of the first bus cycle, the status register command outputs the contents of the status registers synchronized to the falling edge of the clock (SCK) with which the eighth bit of (05h) has been input. In terms of the output sequence, SRWP (bit 7) is the first to be output, and each time one clock is input, all the other bits up to RDY (bit 0) are output in sequence, synchronized to the falling clock edge. If the clock input is continued after RDY (bit 0) has been output, the data is output by returning to the bit (SRWP) that was first output, after which the output is repeated for as long as the clock input is continued. The data can be read by the status register read command at any time (even during a program or erase cycle). Figure 5 Status Register Read CS SCK SI SO MSB MSB MSB 05h DATA DATA High Impedance 8 3 2 1 0 7 6 5 4 15 23 Mode 3 Mode 0 8CLK 16 DATA MSB |
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