LE25U20AQG

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2-2. Status Register Write

The information in status registers BP0, BP1, and SRWP can be rewritten using the status register write command.

RDY, WEN, bit 4, bit 5, and bit 6 are read-only bits and cannot be rewritten. The information in bits BP0, BP1, and

SRWP is stored in the non-volatile memory, and when it is written in these bits, the contents are retained even at power-

down. "Figure 7 Status Register Write" shows the timing waveforms of status register write, and Figure 20 shows a

status register write flowchart. Consisting of the first and second bus cycles, the status register write command initiates

the internal write operation at the rising CS edge after the data has been input following (01h). Erase and program are

performed automatically inside the device by status register write so that erasing or other processing is unnecessary

before executing the command. By the operation of this command, the information in bits BP0, BP1, and SRWP can be

rewritten. Since bits RDY (bit 0), WEN (bit 1), bit 4, bit 5, and bit 6 of the status register cannot be written, no problem

will arise if an attempt is made to set them to any value when rewriting the status register. Status register write ends can

be detected by RDY of status register read. Information in the status registers can be rewritten 1,000 times (min.). To

initiate status register write, the logic level of the WP pin must be set high and status register WEN must be set to "1".

Figure 7 Status Register Write

2-3. Contents of Each Status Register

RDY (bit 0)

The RDY register is for detecting the write (program, erase and status register write) end. When it is "1", the device is

in a busy state, and when it is "0", it means that write is completed.

tSRW

Self-timed

Write Cycle

SCK

SI

High Impedance

SO

CS

DATA

01h

15

0 1 2 3 4 5 6 7 8

Mode3

Mode0

8CLK

WP

tWPH

tWPS