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ISO5852SDWR Datasheet(PDF) 5 Page - Texas Instruments |
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ISO5852SDWR Datasheet(HTML) 5 Page - Texas Instruments |
5 / 37 page ISO5852S www.ti.com SLLSEQ0A – AUGUST 2015 – REVISED SEPTEMBER 2015 7.4 Thermal Information DW (SOIC) THERMAL METRIC(1) UNIT 16 PINS RθJA Junction-to-ambient thermal resistance 99.6 RθJC(top) Junction-to-case (top) thermal resistance 48.5 RθJB Junction-to-board thermal resistance 56.5 °C/W ψJT Junction-to-top characterization parameter 29.2 ψJB Junction-to-board characterization parameter 56.5 (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. 7.5 Power Rating VALUE UNIT PD Maximum power dissipation(1) VCC1 = 5.5-V, VCC2 = 30-V, TA = 25°C 1255 PID Maximum Input power dissipation VCC1 = 5.5-V, VCC2 = 30-V, TA = 25°C 175 mW POD Maximum Output power dissipation VCC1 = 5.5-V, VCC2 = 30-V, TA = 25°C 1080 (1) Full chip power dissipation is de-rated 10.04 mW/°C beyond 25°C ambient temperature. At 125°C ambient temperature, a maximum of 251 mW total power dissipation is allowed. Power dissipation can be optimized depending on ambient temperature and board design, while ensuring that Junction temperature does not exceed 150°C. 7.6 Electrical Characteristics Over recommended operating conditions unless otherwise noted. All typical values are at TA = 25°C, VCC1 = 5 V, VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOLTAGE SUPPLY Positive-going UVLO1 threshold voltage VIT+(UVLO1) 2.25 V input side Negative-going UVLO1 threshold voltage VIT-(UVLO1) 1.7 V input side UVLO1 Hysteresis voltage (VIT+ – VIT–) VHYS(UVLO1) 0.2 V input side Positive-going UVLO2 threshold voltage VIT+(UVLO2) 12 13 V output side Negative-going UVLO2 threshold voltage VIT-(UVLO2) 9.5 11 V output side UVLO2 Hysteresis voltage (VIT+ – VIT–) VHYS(UVLO2) 1 V output side IQ1 Input supply quiescent current 2.8 4.5 mA IQ2 Output supply quiescent current 3.6 6 mA LOGIC I/O Positive-going input threshold voltage (IN+, VIT+(IN,RST) 0.7 x VCC1 V IN-, RST) Negative-going input threshold voltage VIT-(IN,RST) 0.3 x VCC1 V (IN+, IN-, RST) VHYS(IN,RST) Input hysteresis voltage (IN+, IN-, RST) 0.15 x VCC1 V IIH High-level input leakage at (IN+)(1) IN+ = VCC1 100 µA IIL Low-level input leakage at (IN-, RST)(2) IN- = GND1, RST = GND1 -100 µA IPU Pull-up current of FLT, RDY V(RDY) = GND1, V(FLT) = GND1 100 µA V(OL) Low-level output voltage at FLT, RDY I(FLT) = 5 mA 0.2 V GATE DRIVER STAGE V(OUTPD) Active output pull-down voltage I(OUTH/L) = 200 mA, VCC2 = open 2 V VOUTH High-level output voltage I(OUTH) = –20 mA VCC2 - 0.5 VCC2 - 0.24 V VOUTL Low-level output voltage I(OUTL) = 20 mA VEE2 + 13 VEE2 + 50 mV IN+ = high, IN- = low, I(OUTH) High-level output peak current 1.5 2.5 A V(OUTH) = VCC2 - 15 V (1) IIH for IN-, RST pin is zero as they are pulled high internally (2) IIL for IN+ is zero, as it is pulled low internally Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: ISO5852S |
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