Electronic Components Datasheet Search |
|
MPC8266AVR Datasheet(PDF) 4 Page - Motorola, Inc |
|
MPC8266AVR Datasheet(HTML) 4 Page - Motorola, Inc |
4 / 48 page 4 MPC826xA (HiP4) Family Hardware Specifications MOTOROLA Features — Dedicated interface logic for SDRAM • CPU core can be disabled and the device can be used in slave mode to an external core • Communications processor module (CPM) — Embedded 32-bit communications processor (CP) uses a RISC architecture for flexible support for communications protocols — Interfaces to G2 core through on-chip 32-Kbyte dual-port RAM and DMA controller — Serial DMA channels for receive and transmit on all serial channels — Parallel I/O registers with open-drain and interrupt capability — Virtual DMA functionality executing memory-to-memory and memory-to-I/O transfers — Three fast communications controllers supporting the following protocols (only FCC1 and FCC2 on the MPC8255): – 10/100-Mbit Ethernet/IEEE 802.3 CDMA/CS interface through media independent interface (MII) – ATM—Full-duplex SAR protocols at 155 Mbps, through UTOPIA interface, AAL5, AAL1, AAL0 protocols, TM 4.0 CBR, VBR, UBR, ABR traffic types, up to 16 K external connections – Transparent – HDLC—Up to T3 rates (clear channel) — Two multichannel controllers (MCCs) (only MCC2 on the MPC8255) – Each MCC handles 128 serial, full-duplex, 64-Kbps data channels.Each MCC can be split into four subgroups of 32 channels each. – Almost any combination of subgroups can be multiplexed to single or multiple TDM interfaces up to four TDM interfaces per MCC — Four serial communications controllers (SCCs) identical to those on the MPC860, supporting the digital portions of the following protocols: – Ethernet/IEEE 802.3 CDMA/CS – HDLC/SDLC and HDLC bus – Universal asynchronous receiver transmitter (UART) – Synchronous UART – Binary synchronous (BISYNC) communications – Transparent — Two serial management controllers (SMCs), identical to those of the MPC860 – Provide management for BRI devices as general circuit interface (GCI) controllers in time- division-multiplexed (TDM) channels – Transparent – UART (low-speed operation) — One serial peripheral interface identical to the MPC860 SPI — One inter-integrated circuit (I2C) controller (identical to the MPC860 I2C controller) – Microwire compatible – Multiple-master, single-master, and slave modes — Up to eight TDM interfaces (four on the MPC8255) |
Similar Part No. - MPC8266AVR |
|
Similar Description - MPC8266AVR |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |