CY2305 and CY2309 as PCI and SDRAM Buffers
4
Product Information
The CY2305 Zero Delay Buffer
The CY2305 is a 3.3-volt, five output zero delay buffer in an
8-pin 150-mil SOIC package. This part is intended for buffer-
ing one clock into five clocks for PCI buffering or four clocks
for use with 1 SDRAM module. The CY2305 is the simplest
and easiest to use part in the Cypress zero delay buffer family.
For a discussion of the special features of the CY2305 see
the special features section of this application note, or for the
complete specifications on the CY2305 please refer to the
CY2305/CY2309 data sheet.
The CY2309 Zero Delay Buffer
The CY2309 is a 3.3-volt, nine output zero delay buffer in a
16-pin 150-mil SOIC package. This part is intended for buff-
ering one clock into 9 clocks for PCI buffering or eight clocks
for use with 2 SDRAM modules. For the complete specifica-
tions please refer to the CY2305/CY2309 data sheet.
The CY2309 has several options for shutting down the output
banks or completely shutting down the part to conserve pow-
er. As shown in the table below, the inputs S1 and S2 control
which output banks are driven and the state of the PLL. You
will notice that the CLKOUT output is always driven. This is
because the PLL must have the CLKOUT pin running in order
to maintain phase lock. The CY2309 will also go into a power
down state if the input reference stops as described in the
“Special Features of the Cypress Zero Delay Buffers” section.
VCO
REF
CLK1
CLK2
CLK3
CLK4
CLKOUT
LP
Filter
Phase
Detector
PLL
1
2
3
45
8
7
6
REF
CLK2
CLK1
GND
VDD
CLKOUT
CLK4
CLK3
SOIC
Top View
VCO
EF
CLKA1
CLKA2
CLKA3
CLKA4
CLKOUT
LP
Filter
Phase
Detector
PLL
MUX
Select Input
Decoding
S2
S1
CLKB1
CLKB2
CLKB3
CLKB4
1
2
3
4
13
16
15
14
REF
CLKA1
CLKA2
VDD
CLKA3
CLKOUT
CLKA4
VDD
SOIC
Top View
5
6
7
8
GND
CLKB1
CLKB2
S2
9
12
11
10
CLKB3
GND
CLKB4
S1
Select Input Decoding for CY2309
S2
S1
CLOCK A1–A4
CLOCK B1–B4
CLKOUT[1]
Output Source
PLL Shutdown
0
0
Three-State
Three-State
Driven
PLL
N
0
1
Driven
Three-State
Driven
PLL
N
1
0
Driven
Driven
Driven
Reference
Y
1
1
Driven
Driven
Driven
PLL
N
Note:
1. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the delay between the
reference and the CLKA/CLKB outputs.
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