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HM62256AFP-10T Datasheet(PDF) 8 Page - Hitachi Semiconductor |
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HM62256AFP-10T Datasheet(HTML) 8 Page - Hitachi Semiconductor |
8 / 11 page Read Timing Waveform (3) *3 *5 *6 Write Cycle HM62256A-8 HM62256A-10 HM62256A-12 HM62256A-15 —————– —————– —————– —————– Parameter Symbol Min Max Min Max Min Max Min Max Unit Note ———————————————————————————————————————————————– Write cycle time tWC 85 — 100 — 120 — 150 — ns ———————————————————————————————————————————————– Chip selection to tCW 75 — 80 — 85 — 100 — ns 2 end of write ———————————————————————————————————————————————– Address setup time tAS 0— 0— 0— 0— ns 3 ———————————————————————————————————————————————– Address valid to tAW 75 — 80 — 85 — 100 — ns end of write ———————————————————————————————————————————————– Write pulse width tWP 55 — 60 — 70 — 90 — ns 1 ———————————————————————————————————————————————– Write recovery time tWR 0— 0— 0— 0— ns 4 ———————————————————————————————————————————————– WE to output in high-Z tWHZ 0 30 0 35 0 40 0 50 ns 10 ———————————————————————————————————————————————– Data to write time tDW 40 — 40 — 50 — 60 — ns overlap ———————————————————————————————————————————————– Data hold from tDH 0— 0— 0— 0— ns write time ———————————————————————————————————————————————– Output active from tOW 5— 5— 5— 5— ns 10 end of write ———————————————————————————————————————————————– Output disable to tOHZ 0 30 0 35 0 40 0 50 ns 10, 11 output in high-Z ———————————————————————————————————————————————– tACS tCLZ tCHZ Dout CS Valid Data *2 *1,*2 Notes: 1. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. This parameter is sampled and not 100% tested. 3. WE is high for read cycle. 4. Device is continuously selected, CS = VIL. 5. Address Valid prior to or coincident with CS transition Low. 6. OE = VIL. 8 HM62256A Series HM62256A Series |
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