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TLV5619-EP Datasheet(PDF) 1 Page - Texas Instruments |
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TLV5619-EP Datasheet(HTML) 1 Page - Texas Instruments |
1 / 26 page TLV5619EP 2.7 V TO 5.5 V 12BIT PARALLEL DIGITALTOANALOG CONVERTER WITH POWER DOWN SGLS124A − JULY 2002 − REVISED DECEMBER 2003 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D Controlled Baseline − One Assembly/Test Site, One Fabrication Site D Extended Temperature Performance of −40 °C to 125°C D Enhanced Diminishing Manufacturing Sources (DMS) Support D Enhanced Product Change Notification D Qualification Pedigree† D Single Supply 2.7-V to 5.5-V Operation D ±0.4 LSB Differential Nonlinearity (DNL), ±1.5 LSB Integral Nonlinearity (INL) D 12-Bit Parallel Interface D Compatible With TMS320 DSP D Internal Power On Reset D Settling Time 1 µs Typ D Low Power Consumption: − 8 mW for 5-V Supply − 4.3 mW for 3-V Supply D Reference Input Buffers D Voltage Output D Monotonic Over Temperature D Asynchronous Update † Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. applications D Battery Powered Test Instruments D Digital Offset and Gain Adjustment D Battery Operated/Remote Industrial Controls D Machine and Motion Control Devices D Cordless and Wireless Telephones D Speech Synthesis D Communication Modulators D Arbitrary Waveform Generation description The TLV5619 is a 12-bit voltage output DAC with a microprocessor and TMS320 compatible parallel interface. The 12 data bits are double buffered so that the output can be updated asynchronously using the LDAC pin. During normal operation, the device dissipates 8 mW at a 5-V supply and 4.3 mW at a 3-V supply. The power consumption can be lowered to 50 nW by setting the DAC to power-down mode. The output voltage is buffered by a ×2 gain rail-to-rail amplifier, which features a Class A output stage to improve stability and reduce settling time. ORDERING INFORMATION TA PACKAGE‡ ORDERABLE PART NUMBER TOP-SIDE MARKING −40 °C to 125°C SOP − DW Tape and reel TLV5619QDWREP TLV5619QEP ‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Copyright 2002 − 2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D1 D0 CS WE LDAC PD GND OUT REFIN VDD DW PACKAGE (TOP VIEW) |
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