TLV5614EP

2.7V TO 5.5V 12BIT 3 µs QUADRUPLE DIGITALTOANALOG CONVERTER

WITH POWER DOWN

SGLS355 − JUNE 2006

6

POST OFFICE BOX 655303

static DAC specifications

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Resolution

12

bits

Integral nonlinearity (INL), end point adjusted

See Note 1

±1.5

±4

LSB

Differential nonlinearity (DNL)

See Note 2

±0.5

±1

LSB

EZS

Zero-scale error (offset error at zero scale)

See Note 3

±12

mV

Zero-scale error temperature coefficient

See Note 4

10

ppm/

°C

EG

Gain error

See Note 5

±0.7

% of FS

voltage

Gain-error temperature coefficient

See Note 6

10

ppm/

°C

PSRR

Power-supply rejection ratio

Zero scale

See Note 7 and Note 8

−80

dB

PSRR

Power-supply rejection ratio

Full scale

See Note 7 and Note 8

−80

dB

NOTES:

1. The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output

from the line between zero and full scale excluding the effects of zero code and full-scale errors.

2. The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal

1-LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains

constant) as a change in the digital input code.

3. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.

4. Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (Tmax) − EZS (Tmin)E/Vref × 106/(Tmax − Tmin).

5. Gain error is the deviation from the ideal output (2 Vref − 1 LSB) with an output load of 10 kΩ, excluding the effects of the zero error.

6. Gain temperature coefficient is given by: EG TC = [EG(Tmax) − EG (Tmin)]/Vref × 106/(Tmax − Tmin).

7. Zero-scale-error rejection ratio (EZS-RR) is measured by varying the AVDD from 5 ± 0.5 V and 3 ± 0.3 V dc, and measuring the

proportion of this signal imposed on the zero-code output voltage.

8. Full-scale rejection ratio (EG-RR) is measured by varying the AVDD from 5 ± 0.5 V and 3 ± 0.3 V dc and measuring the proportion

of this signal imposed on the full-scale output voltage after subtracting the zero-scale change.

individual DAC output specifications

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VO

Voltage output range

RL = 10 kΩ

0

AVDD−0.4

V

Output load regulation accuracy

RL = 2 kΩ vs 10 kΩ

0.1

0.25

% of FS

voltage

reference inputs (REFINAB, REFINCD)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VI

Input voltage range

See Note 1

0

AVDD−1.5

V

RI

Input resistance

10

M

Ω

CI

Input capacitance

5

pF

Reference feed through

REFIN = 1 VPP at 1 kHz + 1.024 Vdc

(see Note 2)

−75

dB

Reference input bandwidth

REFIN = 0.2 VPP + 1.024-Vdc large signal

Slow

0.5

MHz

Reference input bandwidth

REFIN = 0.2 VPP + 1.024-Vdc large signal

Fast

1

MHz

NOTES:

1. Reference input voltages greater than VDD/2 cause output saturation for large DAC codes.

2. Reference feedthrough is measured at the DAC output, with an input code = 000 hex and a Vref (REFINAB or REFINCD)

input = 1.024 Vdc + 1 VPP at 1 kHz.