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M37210M3-902SP Datasheet(PDF) 9 Page - Mitsubishi Electric Semiconductor

Part # M37210M3-902SP
Description  SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER?
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Manufacturer  MITSUBISHI [Mitsubishi Electric Semiconductor]
Direct Link  http://www.mitsubishichips.com
Logo MITSUBISHI - Mitsubishi Electric Semiconductor

M37210M3-902SP Datasheet(HTML) 9 Page - Mitsubishi Electric Semiconductor

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MITSUBISHI MICROCOMPUTERS
M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP
M37210E4-XXXSP/FP, M37210E4SP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
9
Table 1. Interrupt vector addresses and priority
Interrupt sources
Reset
CRT interrupt
INT2 interrupt
INT1 interrupt
Timer 4 interrupt
f(XIN)/4096 interrupt
VSYNC interrupt
Timer 3 interrupt
Timer 2 interrupt
Timer 1 interrupt
Serial I/O interrupt
BRK instruction interrupt
Remarks
Non-maskable
Active edge selectable
Active edge selectable
Active edge selectable
Non-maskable software interrupt
INTERRUPTS
Interrupts can be caused by 12 different sources consisting of 3 ex-
ternal, 7 internal, 1 software, and reset.
Interrupts are vectored interrupts with priorities shown in Table 1. Re-
set is also included in the table because its operation is similar to an
interrupt.
When an interrupt is accepted, the registers are pushed, interrupt
disable flag I is set, and the program jumps to the address specified
in the vector table. The interrupt request bit is cleared automatically.
The reset can never be disabled. Other interrupts are disabled when
the interrupt disable flag is set.
Priority
1
2
3
4
5
6
7
8
9
10
11
12
Vector addresses
FFFF16, FFFE16
FFFD16, FFFC16
FFFB16, FFFA16
FFF916, FFF816
FFF516, FFF416
FFF316, FFF216
FFF116, FFF016
FFEF16, FFEE16
FFED16, FFEC16
FFEB16, FFEA16
FFE916, FFE816
FFDF16, FFDE16
All interrupts except the BRK instruction interrupt have an interrupt
request bit and an interrupt enable bit. The interrupt request bits are
in interrupt request registers 1 and 2 and the interrupt enable bits are
in interrupt control registers 1 and 2. Figure 4 shows the structure of
the interrupt request registers 1 and 2 and interrupt control registers
1 and 2.
Interrupts other than the BRK instruction interrupt and reset are ac-
cepted when the interrupt enable bit is “1”, interrupt request bit is “1”,
and the interrupt disable flag is “0”. The interrupt request bit can be
reset with a program, but not set. The interrupt enable bit can be set
and reset with a program.
Reset is treated as a non-maskable interrupt with the highest priority.
Figure 5 shows interrupts control.


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